tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 25

• Manufacturer Part Number: tmp19a61f10xbg
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

5.3.2 Clock Gear
Fig. 5.3.2 shows a system clock transition diagram.
X1
X2
fsys
•
•
fperiph
SYSCR0
High
speed
oscillator
<XEN>
Divides high speed clock into 1/1, 1/2, 1/4 and 1/8.
The internal I/O prescaler clock φ T0: fperiph/2, fperiph/4, fperiph/8 and fperiph/16
fosc
fsys/2
Fig. 5.3.2 System Clock Transition Diagram
PLLSEL
SYSCR0<WUEF>
SYSCR2<WUPT1 : 0>
÷2 ÷4 ÷8 ÷16
PLL
Warm-up timer
TMP19A61(rev 1.0)-5-24
SYSCR3 <SCOSEL1:0>
fpll = fosc × 4
2-phase pulse
input counter
<PRCK1:0>
SYSCR0
fc
1/2 1/4 1/8
ADC conversion
ΦT0
clock
SYSCR1 <GEAR2 : 0>
Eight frequency divisions after
the reset has been performed
fgear
DMAC
CPU
INTC
ROM
RAM
÷2
prescaler
SCOUT
Input to peripheral I/O
SYSCR1 <FPSEL>
TMRB/C, SIO, SBI,
TMP19A61
Peripheral I/O
counter
ADC,TMRB/C, SIO, SBI,
WDT, Port, KWUP,
2-phase
fsys
fperiph
to (peripheral
I/O)
pulse
input