tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 252

• Manufacturer Part Number: tmp19a61f10xbg
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

10.4 Functions
10.4.1 Overview
(2) Bus control arbitration (bus arbitration)
(1) Source and destination
(Note 1) Do not bring the TX19A to a halt when the DMAC is in operation.
(Note 2) Stop the DMAC before putting the TX19A into IDLE (doze) mode while snoop
function is active.
The DMAC is a 32-bit DMA controller capable of transferring data in a system using the TX19A
processor core at high speeds without routing data via the core.
In response to a transfer request made inside the DMAC, the DMAC requests the TX19A processor
core to arbitrate bus control authority. When a response signal is returned from the core, the DMAC
acquires bus control authority and executes a data transfer bus cycle.
In acquiring bus control for the DMAC, use or nonuse of the data bus of the TX19A processor core
can be specified; specifically either snoop mode or non-snoop mode can be specified for each
channel by using bit 11 (SReq) of the CCRn register.
There are cases in which the TX19A processor core requests the release of bus control authority.
Whether or not to respond to this request can be specified for each channel by using the bit 10
(RelEn) of the CCRn register. However, this function can only be used in non-snoop mode (GREQ). In
snoop mode (SREQ), the TX19A processor core cannot request the release of bus control; therefore
this function cannot be used.
When there are no more transfer requests, the DMAC releases the bus control.
The DMAC handles data transferred within memory space. A device where the data is output is called
a source device and a device where the data is input is called a destination device. The memory
device can be designated as a source or destination device.
is generated, the interrupt controller (INTC) issues a request to the DMAC (the TX19A processor core
is not notified of the interrupt request. For details, see description on Interrupts.). The request issued
by the INTC is cleared by the DACKn signal. Therefore, a request made to the DMAC is cleared after
completion of each data transfer (transfer of the amount of data specified by TrSiz) if a single transfer
is designated to select a transfer type (SIO BIT). On the other hand, the DACKn signal is asserted
only when the number of bytes transferred (value set in the BCRn register) becomes "0" at a
continuous transfer. Therefore, one transfer request allows data to be transferred successively
without a pause.
For example, if data is transferred between an internal I/O and the internal (external) memory of the
TMP19A61, a request made by the internal I/O to the DMAC is cleared after completion of each data
transfer. The transfer operation is always put in a standby mode for the next transfer request unless
the number of bytes transferred (value set in the BCRn register) becomes "0." Therefore, the DMA
transfer operation continues until the value of the BCRn register becomes "0."
An interrupt factor can be attached to a transfer request to be sent to the DMAC. If an interrupt factor
TMP19A61 (rev1.0)10-251
TMP19A61