tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 328

• Manufacturer Part Number: tmp19a61f10xbg
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

13.3.12 Transmit FIFO Buffer
13.3.13 Transmit FIFO Operation
Transmit buffer 1
In addition to the double buffer function already described, data may be stored using the
transmit FIFO buffer. By setting <CNFG> of the SC0FCNF register and <FDPX1:0> of the
SC0MOD1 register, the 4-byte transmit buffer can be enabled. In the UART mode or I/O
interface mode, up to 4 bytes of data may be stored.
If data is to be transmitted with a parity bit in the UART mode, parity check must be performed
on the receive side each time a data frame is received.
The following example describes the case a 4-byte data stream is transmitted:
SC0TFC <7:6> = 01: Clears transmit FIFO and sets the condition of interrupt generation
SC0TFC <1:0> = 00: Sets the interrupt to be generated at fill level 0.
SC0FCNF <1:0> = 01011: Inhibits continued transmission after reaching the fill level.
In this condition, data transmission can be initiated by setting the transfer mode to half duplex,
writing 4 bytes of data to the transmit FIFO, and setting the <TXE> bit to "1." When the last
transmit data is moved to the transmit buffer, the transmit FIFO interrupt is generated. When
transmission of the last data is completed, the clock is stopped and the transmission
sequence is terminated.
Transmit buffer 2
I/O interface mode with SCLK output (normal mode):
Transmit FIFO
TBEMP
INTTX0
TXE
Fig. 13.3.13.1 Transmit FIFO Operation
Data 6
Data 5
Data 4
Data 3
Data 2
Data 1
TMP19A61 (rev1.0)-13-327
Data 3
Data 6
Data 5
Data 4
Data 2
Data 4
Data 6
Data 5
Data 3
Data 5
Data 6
Data 4
Data 6
Data 5
TMP19A61