tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 59

• Manufacturer Part Number: tmp19a61f10xbg
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

6.9.1.4
(Note 1) This method is recommended for 32 bit ISA because it enables the minimum code increase
(Note 2) This method is recommended for 16 bit ISA because it enables the minimum code increase
(Note 1) The above examples assume use of Assembler made by Toshiba. If any third party
the settings described in Section 6.9.1 "Initialization for Interrupts." When interrupts are disabled, any
interrupt request will be suspended. Also note that TMP19A43 doesn't suspend any interrupt factor that
is set to interrupt level 0.
By these settings, interrupts are disabled immediately after execution of the instruction and the registers
are set two clocks later.
Status <ERL> and <EXL> of CP0 register are automatically set by an interrupt or an exception and
cleared by ERET instruction. These bits are automatically cleared by ERET instruction. Therefore we
recommend setting Status <IE> of CP0 register to “0” to prohibit normal interrupts. Please refer to “6.9.3
Example of Multiple Interrupt Setting” for disabling interrupts using multiple interrupt. Note that one of
the following methods may be used in setting Status <IE> of the CP0 register to "0."
If the factors once enabled are to be individually disabled again after setting interrupt levels by IMCx
<ILxxx> of INTC, first set the Status <ERL/EXL/EI> bits of the CP0 register to disable interrupts and then
disable relevant factors individually.
Example statements to individually disable interrupt factors:
To disable interrupts, either one of the following setting procedures must be performed in addition to
mtc0
sb
sync
mtc0
and high speed processing. If Toshiba C compiler is used, this instruction is executed by
the 32 bit ISA instruction "_ _DI ( ) embedded function."
and high speed processing. If Toshiba C compiler is used, this instruction is executed by
the 32 bit ISA instruction "_ _DI ( ) embedded function."
Assembler is used, it may generate syntax errors; you are advised to modify the above
statements according to the Assembler to be used.
Interrupt Disable
・ Set Status <ERL> of the CP0 register to "1."
・ Set Status <EXL> of the CP0 register to "1."
・ Set Status <IE> of the CP0 register to "0."
1.
2.
3.
4.
r0, IER
r0, IMCxx
r29, IER
Set Status <IE> of the CP0 register to "0" using the MTC0 instruction of 32 bit ISA.
Set IER of the CP0 register to "0" using the MTC0 instruction of 32 bit ISA. (Note 1)
Set Status <IE> of CP0 register to “0” using 16 bit ISA.
Execute DI instruction of 16 bit ISA (Note 2)
TMP19A61(rev1.0)-6-58
; Interrupt is disabled (Status<IE> =”0”).
; Interrupt factor is disabled.
; Stall until it is write-enabled.
; Interrupt is enabled (Status<IE> =”1”).
TMP19A61