tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 568

• Manufacturer Part Number: tmp19a61f10xbg
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

24.9 Serial Channel Timing
*SCLK rise or fall: Measured relative to the programmed active edge of SCLK.
Output mode/
active-high input
mode
Active-low input
mode
OUTPUT DATA
SCLK period
TxD data to SCLK rise or fall*
TxD data hold after SCLK rise or fall*
RxD data valid to SCLK rise or fall*
RxD data hold after SCLK rise or fall*
SCLK period (programmable)
TxD data to SCLK rise
TxD data hold after SCLK rise
RxD data valid to SCLK rise
RxD data hold after SCLK rise
INPUT DATA
(1) I/O Interface mode (DVCC3=1.65V~3.3V)
SCLK
SCLK
RxD
TxD
In the table below, the letter x represents the fsys cycle period, which varies depending on the
programming of the clock gear function.
Parameter
Parameter
SCLK input mode (SIO0~SIO8)
SCLK output mode (SIO0~SIO8)
t
t
OSS
SRD
VALID
0
t
0
SCY
TMP19A61 (rev 1.0)-24-567
Symbol
Symbol
t
t
t
t
t
SCY
OSS
OHS
SRD
HSR
t
t
t
t
t
OSS
OHS
SRD
HSR
SCY
2x+29
2x-35
8x-15
4x-14
4x-14
Min
Min
12x
VALID
30
8x
45
Equation
Equation
0
1
1
t
HSR
t
OHS
Max
Max
Min
Min
222
133
222
30
66
60
60
45
2
0
54 MHz
54 MHz
VALID
2
2
Max
Max
TMP19A61
Unit
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
VALID
3
3