tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 58

• Manufacturer Part Number: tmp19a61f10xbg
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

6.9.1.3
(Note 1) This method is recommended for 32 bit ISA because it enables the minimum code increase
(Note 2) This method is recommended for 16 bit ISA because it enables the minimum code increase
By these settings, interrupt is enabled two clocks after execution of the instruction and the registers are
set. Note that one of the following four methods may be used in setting Status <IE> of the CP0 register
to "1."
In order for an interrupt request to be accepted, all the following three parameters must be set to
enable the interrupt in addition to the initial settings described in Section 6.9.11 "Initialization for
Interrupts".
and high speed processing. If Toshiba C compiler is used, this is executed by the 32 bit ISA
instruction "_ _EI ( ) embedded function."
and high speed processing. If Toshiba C compiler is used, this instruction is executed by
the 16 bit ISA instruction "_ _EI ( ) embedded function."
Interrupt Enable
・ Status <ERL> of the CP0 register is set to "0."
・ Status <EXL> of the CP0 register is set to "0."
・ Status <IE> of the CP0 register is set to "1."
1.
2.
3.
4.
Set Status<IE> of the CP0 register to “1” using the MTC0 instruction (32 bit ISA
instruction)
Set IER of the CP0 register to any value other than "0" using the MTC0 instruction (32 bit
ISA instruction). (Note 1)
Set Status<IE> of the CP0 register to “1” using the MTC0 instruction (16 bit ISA
instruction).
Execute the EI instruction of 16 bit ISA. (Note 2)
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