tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 393
tmp19a61f10xbg
Manufacturer Part Number
tmp19a61f10xbg
Description
32-bit Tx System Risc Tx19 Family
Manufacturer
TOSHIBA Semiconductor CORPORATION
Datasheet
1.TMP19A61F10XBG.pdf
(575 pages)
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Part Number:
TMP19A61F10XBG
Manufacturer:
TOSHIBA/东芝
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15. Serial Bus Interface (SBI)
The configuration is shown in Fig. 15.1.
I
Clock-synchronous
8- bit SIO mode
2
C bus mode
15.1 Configuration
SBI0 control register 2/
SBI0 status register
fsys/4
The TMP19A61 contains two Serial Bus Interface (SBI) channels; CH0 and CH1 that operate
identically (only CH0 is described here). The Serial Bus Interfaces have the following two operation
modes.
The following table shows the programming required to put the SBI in each operating mode.
•
•
In the I
clock-synchronous 8-bit SIO mode, the SBI is connected to external devices via PE7 (SCK), PE5
(SO) and PE6 (SI).
X: Don’t care
I
Clock-synchronous 8-bit SIO mode
2
C bus mode (with multi-master capability)
synchroniz
SBI0CR2/
2
Frequency
SBI0SR
I
C bus mode, the SBI is connected to external devices via PE5 (SDA) and PE6 (SCL). In the
control
ation +
control
2
clock
clock
divider
C bus
SIO
111 (clock input)
011 (clock output)
PEIE <7:5>
I
address register
X11
2
C bus
Transfer
I2CAR
control
circuit
TMP19A61
Fig. 15.1 SBI Block Diagram
PESEL<7:5>
XXX
SBI0 data
buffer register
111
INTSBI initerrupt
SBI0DBR
register
Shift
(
rev1.0
PEOD<6:5>
SBI0 control registers
)
-15-392
11
00
SBI0CR0,1
data control
data control
I
0,1
2
C bus
SIO
PEFC1<7:5>
SBI0 baud rate reigsters
X11
111
SBI0BR0, 1
canceller
canceller
Noise
Noise
TMP19A61
0, 1
111 (clock input)
011 (clock output)
SCL
SCK
SO
SI
SDA
control
output
Input/
PECR<7:5>
X11
(SCK)
(SO/SDA)
(SI/SCL)
PE7
PE5
PE6
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