tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 359

• Manufacturer Part Number: tmp19a61f10xbg
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

•
* Clocking conditions
* Clocking conditions
1) Division by an integer (divide by N)
1) For divide by N + (16-K)/16 (only for UART mode)
(Note) The divide by (N + (16-K)/16) function is inhibited and thus HBR0ADD
2) I/O interface mode
Examples of baud rate setting:
The highest baud rate will be generated when fsys is 54 MHz. If double buffering is
used, the divide ratio can be set to "2" and the resulting output baud rate will be 13.5
Mbps. If double buffering is not used, the highest baud rate will be 6.75 Mbps applying
the divide ratio of "4".
Using the baud rate generator input clock sys, setting the divide ratio N
(HBR0CR<BR0S5:0>) = 4, and setting HBR0CR<BR0ADDE> = "0," the resulting
baud rate in the UART mode is calculated as follows:
Using the baud rate generator fsys, setting the divide ratio N (HBR0CR<BR3S5:0>) =
4, setting K (HBR0ADD<BR3K3:0>) = 14, and selecting HBR0CR<BR3ADDE> = 1,
the resulting baud rate is calculated as follows:
Baud rate =
= 54 × 10
Baud rate =
= 54 × 10
Baud rate =
<BR0K3:0> is ignored.
6
6
÷ 4 ÷ 16 = 843.8k (bps)
÷ ( 4 +
fsys
4
TMP19A61(rev. 1.0) 14-358
4
Frequency
+
÷ 16
Fsys
16
2
System clock: high-speed (fc)
System clock
High-speed clock gear: x1 (fc)
High-speed clock gear:x1 (fc)
(16-14)
) ÷ 16 = 818.2K (bps)
16
divided
÷
fsys
by the
16
divide
:High-speed (fc)
ratio
÷ 2
TMP19A61