tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 282

• Manufacturer Part Number: tmp19a61f10xbg
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

TBnCR
(0xFFFF_Fxx1)
TBnMOD
(0xFFFF_Fxx2)
registers in the TMRB module. This can reduce power consumption. (This disables reading from and writing
to the other registers.) To use the TMRB, enable the TMRB operation (set to “1”) before programming each
register in the TMRB module. If the TMRB operation is executed and then disabled, the settings will be
maintained in each register.
＜TBnEN＞: Specifies the TMRB operation. When the operation is disabled, no clock is supplied to the other
＜TBnCLK1:0＞: Selects the TMRBn timer count clock.
＜TBnCLE＞: Clears and controls the TMRBn up-counter.
＜TBnCPM1:0＞: Specifies TMRBn capture timing.
<TBnCP0>:Captures count values by software and takes them into capture register 0 (TBnCP0).
<TBnRSWR>: Controls writing timing to timer registers 0 and 1 when using double buffer.
(Note) The value read from bit 5 of TBnMOD is “1”.
“0”:Writing to the timer registers 0 and 1 is enabled individually if either of them is ready to be written.
“1”:Writing to the timer registers 0 and 1 is enabled only when both are ready to be written.
“0” : Disables clearing of the up-counter.
“1” : Clears up-counter if there is a match with timer register 1 (TBnRG1).
“00” : Capture disable
“01” :Takes count values into capture register 0 (TBnCP0) upon rising of TBnIN0 pin input. Takes
“10” :Takes count values into capture register 0 (TBnCP0) upon rising of TBnIN0 pin input. Takes
“11” :Takes count values into capture register 0 (TBnCP0) upon rising of timer output for capture
Bit symbol
Read/Write
After reset
Bit symbol
Read/Write
After reset
Function
Function
count values into capture register 1 (TBnCP1) upon rising of TBnIN1 pin input.
count values into capture register 1 (TBnCP1) upon falling of TBnIN0 pin input.
trigger (CAPTRG) and into capture register 1 (TBnCP1) upon falling of CAPTRG (CAPTRG
for TMRB08 ~ 0F: TB1OUT, for TMRB10 ~ 13: TB2OUT).
TMRBn
operation
0: Disable
1: Enable
This
be read as
“0”.
TBnEN
R/W
TMRBn mode register（n=00 ~ 23, except for 0C and 12）
7
7
R
0
0
can
Write “0”.
Writing to
timer
registers
0,1
0：Always
enabled
1:Enabled
simultaneou
sly
RSWR
TBｎ
R/W
R/W
6
6
0
0
TMRBn control register（n=00 ~ 23）
TMP19A61 (rev 1.0)11-281
1: Don't care
Capture
control by
software
0: Capture
by software
This can
be read as
“0”.
TBnCP0
W
R
5
5
1
0
00: Disable
01: TBnIN0 ↑ TBnIN1 ↑
10: TBnIN0 ↑ TBnIN0 ↓
11: CAPTRG ↑ CAPTRG ↓
Capture timing
This can
be read as
“0”.
TBnCPM1 TBnCPM0
4
R
4
0
0
This can be
read as “0”.
3
R
3
0
0
0: Clear/
1: Clear/
This can
be read as
“0”.
Up-counter
control
TBnCLE
disable
enable
R/W
2
R
0
2
0
This can
be read as
“0”.
Selects source clock
00: TBnIN0 pin input
01: φT1
10: φT4
11: φT16
TBnCLK1
1
R
0
1
TMP19A61
0
This can
be read as
“0”.
TBnCLK0
R
0
0
0
0