tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 31

• Manufacturer Part Number: tmp19a61f10xbg
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

5.8 Standby Controller
The TX19A core has several low-consumption modes. To shift to the STOP or IDLE (Halt or
Doze) mode, set the RP bit in the CPO status register, and then execute the WAIT instruction.
Before shifting to the mode, you need to select the standby mode at the system control register
(SYSCR2).
The IDLE and STOP modes have the following features:
IDLE: Only the CPU is stopped in this mode.
STOP: All the internal circuits are brought to a stop.
(Note 1) The Halt mode is activated by setting the RP bit in the status register to
(Note 2) The Doze mode is activated by setting the RP bit in the status register to
The internal I/O has one bit of the ON/OFF setting register for operation at the IDLE
mode in the register of each module. This enables operation settings at the IDLE
mode. When the internal I/O has been set not to operate in the IDLE mode, it stops
operation and holds the state when the system enters the IDLE mode.
Table-5.8 shows a list of IDLE setting registers.
Table 5.8 Internal I/O setting registers for the IDLE mode
"0," executing the WAIT command and shifting to the standby mode. In this
mode, the TX19A processor core stops the processer operation while
holding the status of the pipeline. The TX19A gives no response to the bus
control authority request from the internal DMA, so the bus control
authority is maintained in this mode.
"1" and shifting to the standby mode. In this mode, the TX19A processor
core stops the processer operation while holding the status of the pipeline.
The TX19A can respond to the bus control authority request given from the
outside of the processor core.
Internal I/O
TMRB0~23
A/DC A~B
HSIO0~1
TBTA~B
SIO0~9
TMP19A61(rev 1.0)-5-30
WDT
SBI
IDLE mode setting register
HSCxMOD1<I2Sx>
TBTxRUN<I2TBT>
WDMOD<I2WDT>
ADxMOD1<I2AD>
SCxMOD1<I2Sx>
SBIxBR0<I2SBI>
Textron<I2TBx>
TMP19A61