tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 333

• Manufacturer Part Number: tmp19a61f10xbg
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

13.3.20 Signal Generation Timing
Note 1) Do not make any change in control register when data is being sent or
Note 2) Do not stop the receive operation (by setting SC0MOD0 <RXE> = "0") when
Receive Side
Transmit Side
Receive Side
Transmit Side
Note 3) Do not stop the transmit operation (by setting SC0MOD1 <TXE> = "0")
Interrupt generation
timing
Framing error timing
Parity error generation
timing
Overrun error generation
timing
Interrupt generation
timing
Interrupt generation
timing
Interrupt generation
timing
Interrupt generation
timing
Overrun error
generation timing
Interrupt generation
timing
Interrupt generation
timing
Underrun error
generation timing
(<WBUF> = 0)
(<WBUF> = 1)
(<WBUF> = 0)
(<WBUF> = 1)
(<WBUF> = 0)
(<WBUF> = 1)
UART mode
I/O interface mode:
received (in a state ready to transmit or receive).
data is being received.
when data is being transmitted.
Mode
Mode
SCLK output
mode
SCLK input mode Immediately after the rising or falling edge of the last SCLK (for rising
SCLK output
mode
SCLK input mode
SCLKinput mode
SCLK output
mode
SCLK input mode Immediately after the rising or falling edge of the last SCLK (for rising
SCLK output
mode
SCLK input mode Immediately after the rising or falling edge of the last SCLK (for the
SCLK input mode Immediately after the falling or rising edge of the next SCLK (for the
TMP19A61 (rev1.0)-13-332
Around the center
of the 1st stop bit
Around the center
of the stop bit
Around the center
of the stop bit
Just before the stop
bit is sent
Immediately after
data is moved to
transmit buffer 1
(just before start bit
transmission)
9-bit
9-bit
-
Immediately after the rising edge of the last SCLK
or falling edge mode, respectively)
Immediately after the rising edge of the last SCLK (just after data
transfer to receive buffer 2) or just after receive buffer 2 is read
depending on the rising or falling edge triggering mode, respectively
(right after data is moved to receive buffer 2)
Immediately after the rising or falling edge of the last SCLK (for rising
or falling edge mode, respectively)
Immediately after the rising edge of the last SCLK
or falling edge mode, respectively)
Immediately after the rising edge of the last SCLK or just after data is
moved to transmit buffer 1
rising or falling edge mode, respectively) or just after data is moved
to transmit buffer 1
rising or falling edge triggering mode, respectively)
Immediately after the rising edge or falling edge of the last SCLK
Around the center of the
1st stop bit
Around the center of the
stop bit
Around the center of the
last (parity) bit
Around the center of the
stop bit
Just before the stop bit is
sent
Immediately after data is
moved to transmit buffer 1
(just before start bit
transmission)
8-bit + parity
8-bit + parity
Around the center of the 1st stop bit
Around the center of the stop bit
Around the center of the last (parity) bit
Around the center of the stop bit
Just before the stop bit is sent
Immediately after data is moved to
transmit buffer 1 (just before start bit
transmission)
TMP19A61
7-bit + parity, 7-bit
7-bit + parity, 7-bit
8-bit,
8-bit,