tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 207
tmp19a61f10xbg
Manufacturer Part Number
tmp19a61f10xbg
Description
32-bit Tx System Risc Tx19 Family
Manufacturer
TOSHIBA Semiconductor CORPORATION
Datasheet
1.TMP19A61F10XBG.pdf
(575 pages)
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TMP19A61F10XBG
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2 waits automatically inserted
2 waits automatically inserted + 2N (N=1)
By setting the bit 3<P33F1> of port 3 function register1 P3FC1 to "1," the WAIT input pin (P33)
can also serve as the RDY input pin.
The RDY input is input to the external bus interface circuit as the logical reverse of the WAIT
input. The number of waits is specified by the chip selector and a wait controller register,
BmnCS<BnW>.
Fig. 8.7 shows the RDY inputs and the number of waits.
fsys
A[23:0]
D[15:0]
A[23:0]
D[15:0]
/RDY
/RDY
/RD
/RD
Fig. 8.7 RDY Input and Wait Operation Timing Diagram
--- External RDY sampling point
External RDY sampling points take place before a cycle of waits automatically
inserted is finished and before a 2N_wait cycle is finished as shown above.
The same applies to combinations of other numbers of waits.
TMP19A61(rev1.0)-8-206
2 waits automatically
2 waits automatically
tsys
inserted
inserted
2N_WAIT
TMP19A61
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