tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 361

• Manufacturer Part Number: tmp19a61f10xbg
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

14.1.2
14.1.3
14.1.4
14.1.5
High-speed Serial Clock Generation Circuit
Receive Counter
Receive Control Unit
Receive Buffer
•
•
The receive counter is a 4-bit binary counter used in the asynchronous (UART) mode and is
up-counted by HSIOCLK. Sixteen HSIOCLK clock pulses are used in receiving a single
data bit while the data symbol is sampled at the seventh, eighth, and ninth pulses. From
these three samples, majority logic is applied to decide the received data.
•
•
The receive buffer is of a dual structure to prevent overrun errors. Receive Buffer 1 (a shift
register) stores the received data bit-by-bit. When a complete set of bits have been stored,
they are moved to Receive Buffer 2 (HSC0BUF). At the same time, the receive buffer full
flag (HSC0MOD2 "RBFLL") is set to "1" to indicate that valid data is stored in Receive Buffer
2. However, if the receive FIFO is set enabled, the receive data is moved to the receive
FIFO and this flag is immediately cleared.
If
HSC0MOD1<FDPX1:0> = 01), the HINTRX0 interrupt is generated at the same time. If the
receive FIFO has been enabled (HSCNFCNF <CNFG> = 1 and HSC0MOD1<FDPX1:0> ＝
01/11), an interrupt will be generated according to the HSC0RFC <RIL1:0> setting.
output of the previously mentioned baud rate generator is divided by 2 to generate the
basic clock.
This circuit generates basic transmit and receive clocks.
In the HSCLK output mode with the HSC0CR <IOC> serial control register set to "0," the
In the HSCLK output mode with HSC0CR <IOC> set to "0," the HRXD0 pin is sampled
on the rising edge of the shift clock output to the HSCLK0 pin.
In the HSCLK input mode with HSC0CR <IOC> set to "1," rising and falling edges are
detected according to the HSC0CR <SCLKS> setting to generate the basic clock.
According to the settings of the serial control mode register HSC0MOD0 <SC1:0>, either
the clock from the baud rate generator, the system clock (f
of the TMRB8 timer, or the external clock (HSCLKO pin) is selected to generate the
basic clock, HSIOCL.
In the HSCLK input mode with HSC0CR <IOC> set to "1," the serial receive data HRXD0
pin is sampled on the rising or falling edge of HSCLK input depending on the HSC0CR
<SCLKS> setting.
The receive control unit has a start bit detection circuit, which is used to initiate receive
operation when a normal start bit is detected.
the
I/O interface mode
Asynchronous (UART) mode
I/O interface mode
Asynchronous (UART) mode:
receive
FIFO
TMP19A61(rev. 1.0) 14-360
has
been
disabled
(HSCOFCNF
SYS
), the internal output signal
TMP19A61
<CNFG>
=
0
and