tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 111

• Manufacturer Part Number: tmp19a61f10xbg
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

7.6
Port 5 (P50~P57)
The port 5 is a general-purpose, 8-bit input/output port. For this port, inputs and outputs can be
specified in units of bits. Outputs can be set by using the function register P5FC1 and the control
register P5CR. A reset allows all bits of the output latch P5 to be set to "1," all bits of P5CR and
P5FC1 to be cleared to "0," and the port 5 to be put in output disable mode.
The port 5 also functions as an address bus (A0 through A7). To access external memory, P5CR
and P5FC1 must be provisioned to allow the port 5 to function as an address bus.
P5 read
(Function control)
(Output control)
(Output latch)
(Input control)
P5FC1
P5CR
P5IE
P5
A0~A7
TMP19A61(rev1.0)7-110
Fig. 7.11 Port 5 (P50~P57)
STOP/RESET
drive disable
Bus opening
0
1
0
1
TMP19A61
Port 5
P50~P57
A0~A7
RESET