tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 354

• Manufacturer Part Number: tmp19a61f10xbg
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Protocol
Select the 9-bit UART mode for the master and slave controllers.
Set SC0MOD <WU> to "1" for the slave controllers to make them ready to receive data.
The master controller is to send a single frame of data that includes the slave controller
select code (8 bits). In this, the most significant bit (bit 8) <TB8> must be set to "1."
Every slave controller receives the above data frame; if the code received matches with the
controller's own select code, it clears the WU bit to "0."
The master controller transmits data to the designated slave controller (the controller of
which SC0MOD <WU> bit is cleared to "0"). In this, the most significant bit (bit 8) <TB8>
must be set to "0."
The slave controllers with the <WU> bit set to "1" ignore the receive data because the most
significant bit (bit 8) <RB8> is cleared to "0" and thus no interrupt (INTRX0) is generated.
Also, the slave controller with the <WU> bit cleared to "0" can transmit data to the master
controller to inform that the data has been successfully received.
Example setting: Using the internal clock f
start
start
TXD
bit 0
bit 0
Master
controllers are serially linked as follows:
RXD
1
1
TMP19A61 (rev1.0)-13-353
Slave controller select code
2
2
3
3
Data
TXD
4
4
Select code
00000001
Slave 1
5
5
RXD
6
6
SYS
/2 as the transfer clock, two slave
7
7
TXD
Select code
00001010
bit 8
Slave 2
“1”
“0”
8
RXD
stop
stop
TMP19A61