tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 383

• Manufacturer Part Number: tmp19a61f10xbg
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

TMP19A61
HSCLK input mode
In the HSCLK input mode, if HSC0MOD2 <WBUF> is set to "0" and the transmit
double buffers are disabled, 8-bit data that has been written in the transmit buffer is
output from the HTXD0 pin when the HSCLK0 input becomes active. When all 8 bits
are sent, the HINTTX0 interrupt is generated. The next transmit data must be written
before the timing point "A".
If HSC0MOD2 <WBUF> is set to "1" and the transmit double buffers are enabled, data
is moved from Transmit Buffer 2 to Transmit Buffer 1 when the CPU writes data to
Transmit Buffer 2 before the HSCLK0 becomes active or when data transmission from
Transmit Buffer 1 (shift register) is completed. As data is moved from Transmit Buffer 2
to Transmit Buffer 1, the Transmit Buffer empty flag HSC0MOD2 <TBEMP> is set to
"1" and the HINTTX0 interrupt is generated. If the HSCLK0 input becomes active while
no data is in Transmit Buffer 2, the internal bit counter is started; however, an
under-run error occurs and 8-bit dummy data (FFh) is sent.
TMP19A61(rev. 1.0) 14-382