tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 302
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tmp19a61f10xbg
Manufacturer Part Number
tmp19a61f10xbg
Description
32-bit Tx System Risc Tx19 Family
Manufacturer
TOSHIBA Semiconductor CORPORATION
Datasheet
1.TMP19A61F10XBG.pdf
(575 pages)
Available stocks
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Part Number
Manufacturer
Quantity
Price
Part Number:
TMP19A61F10XBG
Manufacturer:
TOSHIBA/东芝
Quantity:
20 000
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peripheral
<FPSEL>
0(fgear)
Select
clock
1(fc)
(Note 1)
(Note 3)
(Note 2)
Clock gear
<GEAR2:0>
100(fc/2)
100(fc/2)
110(fc/4)
111(fc/8)
110(fc/4)
111(fc/8)
000(fc)
000(fc)
value
The prescaler output clock φTn must be selected so that φTn<fsys/2 is satisfied (so
that φTn is slower than fsys/2).
Do not change the clock gear while the timer is operating.
"-" denotes "setting prohibited."
00(fperiph/16)
01(fperiph/8)
10(fperiph/4)
11(fperiph/2)
00(fperiph/16)
01(fperiph/8)
10(fperiph/4)
11(fperiph/2)
00(fperiph/16)
01(fperiph/8)
10(fperiph/4)
11(fperiph/2)
00(fperiph/16)
01(fperiph/8)
10(fperiph/4)
11(fperiph/2)
00(fperiph/16)
01(fperiph/8)
10(fperiph/4)
11(fperiph/2)
00(fperiph/16)
01(fperiph/8)
10(fperiph/4)
11(fperiph/2)
00(fperiph/16)
01(fperiph/8)
10(fperiph/4)
11(fperiph/2)
00(fperiph/16)
01(fperiph/8)
10(fperiph/4)
11(fperiph/2)
clock
Select prescaler
Table 12.1 Prescaler Output Clock Resolutions (2/2)
<PRCK1:0>
TMP19A61 (rev1.0)-12-301
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
10
9
8
7
11
10
9
8
12
11
10
9
13
12
11
10
10
9
8
7
10
9
8
7
10
9
8
7
10
9
8
7
(9.48 µs)
(4.74 µs)
(2.37 µs)
(9.48 µs)
(4.74 µs)
(9.48 µs)
(9.48 µs)
(4.74 µs)
(2.37 µs)
(9.48 µs)
(4.74 µs)
(2.37 µs)
(9.48 µs)
(4.74 µs)
(2.37 µs)
(9.48 µs)
(4.74 µs)
(2.37 µs)
(18.96 µs)
(37.93 µs)
(18.96 µs)
(75.85 µs)
(37.93 µs)
(18.96 µs)
(151.7 µs)
(75.85 µs)
(37.93 µs)
(18.96 µs)
(18.96 µs)
(18.96 µs)
(18.96 µs)
(18.96 µs)
ΦT32
Prescaler output clock resolution
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
11
10
9
8
12
11
10
9
13
12
11
10
14
13
12
11
11
10
9
8
11
10
9
8
11
10
9
8
11
10
9
8
(9.48 µs)
(4.74 µs)
(9.48 µs)
(9.48 µs)
(4.74 µs)
(9.48 µs)
(4.74 µs)
(9.48 µs)
(4.74 µs)
(9.48 µs)
(4.74 µs)
(37.93 µs)
(37.93 µs)
(37.93 µs)
(37.93 µs)
(37.93 µs)
(37.93 µs)
(37.93 µs)
(37.93 µs)
(18.96 µs)
(75.85 µs)
(18.96 µs)
(151.7 µs)
(75.85 µs)
(18.96 µs)
(303.4 µs)
(151.7 µs)
(75.85 µs)
(18.96 µs)
(18.96 µs)
(18.96 µs)
(18.96 µs)
ΦT64
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
12
11
10
9
13
12
11
10
14
13
12
11
15
14
13
12
12
11
10
9
12
11
10
9
12
11
10
9
12
11
10
9
(9.48 µs)
(9.48 µs)
(9.48 µs)
(9.48 µs)
(9.48 µs)
(37.93 µs)
(37.93 µs)
(37.93 µs)
(37.93 µs)
(37.93 µs)
(37.93 µs)
(37.93 µs)
ΦT128
(75.85 µs)
(18.96 µs)
(151.7 µs)
(75.85 µs)
(18.96 µs)
(303.4 µs)
(151.7 µs)
(75.85 µs)
(606.8 µs)
(303.4 µs)
(151.7 µs)
(75.85 µs)
(75.85 µs)
(18.96 µs)
(75.85 µs)
(18.96 µs)
(75.85 µs)
(18.96 µs)
(75.85 µs)
(18.96 µs)
TMP19A61
@fc = 54MHz
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
13
12
11
10
14
13
12
11
15
14
13
12
16
15
14
13
13
12
11
10
13
12
11
10
13
12
11
10
13
12
11
10
(37.93 µs)
(37.93 µs)
(37.93 µs)
(37.93 µs)
(37.93 µs)
(37.93 µs)
(151.7 µs)
(75.85 µs)
(18.96 µs)
(303.4 µs)
(151.7 µs)
(75.85 µs)
(606.8 µs)
(303.4 µs)
(151.7 µs)
(75.85 µs)
(1213.6 µs)
(606.8 µs)
(303.4 µs)
(151.7 µs)
(151.7 µs)
(75.85 µs)
(18.96 µs)
(151.7 µs)
(75.85 µs)
(18.96 µs)
(151.7 µs)
(75.85 µs)
(18.96 µs)
(151.7 µs)
(75.85 µs)
(18.96 µs)
ΦT256
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