tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 228
tmp19a61f10xbg
Manufacturer Part Number
tmp19a61f10xbg
Description
32-bit Tx System Risc Tx19 Family
Manufacturer
TOSHIBA Semiconductor CORPORATION
Datasheet
1.TMP19A61F10XBG.pdf
(575 pages)
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TMP19A61F10XBG
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TMP19A61
9.2 The Chip Selector and Wait Controller
Fig. 9.2.1 through Fig. 9.2.4 show the chip selector and wait controller registers. For each
address space (spaces CS0 through CS5 and other address spaces), each chip selector and
wait controller register (B01CS through B45CS) can be programmed to set master enable or
disable, to select data bus width, to specify the number of waits and to insert dummy cycles.
If two or more address spaces are specified simultaneously, a space or spaces with a smaller
space number will be selected by priority (priority order: CS0>CS1>CS2>CS3>CS4>CS5).
TMP19A61 (rev1.0)-9-227
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