tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 369

• Manufacturer Part Number: tmp19a61f10xbg
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

14.1.13 Parity Control Circuit
I/O interface mode with HSCLK input (normal mode):
Transmit buffer 1
Transmit buffer 2
If the parity addition bit <PE> of the serial control register HSC0CR is set to "1," data is sent
with the parity bit. Note that the parity bit may be used only in the 7- or 8-bit UART mode.
The <EVEN> bit of HSC0CR selects either even or odd parity.
Upon data transmission, the parity control circuit automatically generates the parity with the
data written to the transmit buffer (HSC0BUF). After data transmission is complete, the
parity bit will be stored in HSC0BUF bit 7 <TB7> in the 7-bit UART mode and in bit 7 <TB8>
in the serial mode control register HSC0MOD in the 8-bit UART mode. The <PE> and
<EVEN> settings must be completed before data is written to the transmit buffer.
Upon data reception, the parity bit for the received data is automatically generated while the
data is shifted to Receive Buffer 1 and moved to Receive Buffer 2 (HSC0BUF). In the 7-bit
UART mode, the parity generated is compared with the parity stored in HSC0BUF <RB7>,
while in the 8-bit UART mode, it is compared with the bit 7 <RB8> of the HSC0CR register.
If there is any difference, a parity error occurs and the <PERR> flag of the HSC0CR register
is set.
In the I/O interface mode, the HSC0CR <PERR> flag functions as an under-run error flag,
not as a parity flag.
generation.
the transfer mode to half duplex, writing 4 bytes of data to the transmit FIFO, and setting
the <TXE> bit to "1." When the last transmit data is moved to the transmit buffer, the
transmit FIFO interrupt is generated.
TX FIFO
The following example describes the case a 4-byte data stream is transmitted:
HSC0TFC <1:0> = 01: Clears the transmit FIFO and sets the condition of interrupt
HSC0TFC <7:2> = 000000: Sets the interrupt to be generated at fill level 0.
HSC0FCNF <4:0> = 01001: Allows continued transmission after reaching the fill level.
In this condition, data transmission can be initiated depend on the input clock by setting
TBEMP
INTTX0
TXE
Fig. 14-9 Transmit FIFO Operation
TMP19A61(rev. 1.0) 14-368
Data 6
Data 5
Data 4
Data 3
Data 2
Data 1
Data 5
Data 4
Data 3
Data 2
Data 6
Data 4
Data 6
Data 5
Data 3
Data 5
Data 6
Data 4
Data 6
Data 5
TMP19A61