tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 400

• Manufacturer Part Number: tmp19a61f10xbg
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

15.5
15.5.1
15.5.2
15.5.3
Control in the I
Setting the Acknowledgement Mode
Setting the Number of Bits per Transfer
Serial Clock
The highest speeds in the standard and high-speed modes are
specified to 100KHz and 400KHz respectively in the communications
standards. Note that the internal SCL clock frequency is determined by
the fsys used and the calculation formula shown above.
Setting SBI0CR1<ACK> to "1" selects the acknowledge mode. When operating as a
master, the SBI adds one clock for acknowledgment signals. As a transmitter, the SBI
releases the SDA pin during this clock cycle to receive acknowledgment signals from the
receiver. As a receiver, the SBI pulls the SDA pin to the "L" level during this clock cycle and
generates acknowledgment signals.
Setting <ACK> to "0" selects the non-acknowledgment mode. When operating as a master,
the SBI does not generate clock for acknowledgement signals.
SBI0CR1 <BC2:0> specifies the number of bits of the next data to be transmitted or
received.
Under the start condition, <BC2:0> is set to "000," causing a slave address and the
direction bit to be transferred in a packet of eight bits. At other times, <BC2:0> keeps a
previously programmed value.
Clock source
SBI0CR1 <SCK2:0> specifies the maximum frequency of the serial clock to be output
from the SCL pin in the master mode.
t
t
fscl = 1/(t
LOW
HIGH
=
2
C Bus Mode
= 2
= 2
2
n-1
fsys/2
Low
n-1
n
+ 70
/(fsys/2) + 58/(fsys/2)
/(fsys/2) + 12/(fsys/2)
+ t
HIGH
t
HIGH
TMP19A61
Fig. 15.5.3.1 Clock Source
)
t
LOW
(
rev1.0
SBI0CR1 <SCK2:0>
)
-15-399
000
001
010
011
100
101
110
1/fscl
10
11
n
5
6
7
8
9
TMP19A61