tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 203

• Manufacturer Part Number: tmp19a61f10xbg
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

8.3
External Bus Operations (Separate Bus Mode)
This section describes various bus timing values. The timing diagram shown below assumes
that the address buses are A23 through A0 and that the data buses are D15 through D0.
(1) Basic bus operation
wait can be inserted as mentioned later. The basic clock of an external bus cycle is the
same as the internal system clock.
accessed, address buses remain unchanged as shown in these figures. Additionally, data
buses are in a state of high impedance and control signals such as RD and
become active.
WR
The external bus cycle of the TMP19A61 basically consists of three clock pulses and a
Fig. 8.1 shows read bus timing and Fig. 8.2 shows write bus timing. If internal areas are
CSn
A [23 : 0]
D [15 : 0]
CSn
A [23 : 0]
D [15 : 0]
RD
Fig. 8.1 Read Operation Timing Diagram
Fig. 8.2 Write Operation Timing Diagram
TMP19A61(rev1.0)-8-202
External access
External access
tsys
tsys
DATA
DATA
No output of RD
Internal access
Internal access
Address HOLD
Address HOLD
No output of WR
Output High−Z
Output High−Z
TMP19A61
WR
do not