tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 370

• Manufacturer Part Number: tmp19a61f10xbg
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

14.1.14 Error Flag
1.
2.
3. Framing error <FERR>: Bit 2 of the HSC0CR register:
Three error flags are provided to increase the reliability of received data.
Overrun error <OERR>: Bit 4 of the serial control register HSC0CR
by completing the reception of the next frame receive data before the receive buffer
has been read. If the receive FIFO is enabled, the received data is automatically
moved to the receive FIFO and no overrun error will be generated until the receive
FIFO is full (or until the usable bytes are fully occupied). This flag is set to "0" when it is
read. In the I/O interface HSCLK output mode, no overrun error is generated and
therefore, this flag is inoperative and the operation is undefined.
Parity error/under-run error <PERR>: Bit 3 of the HSC0CR register
In the UART mode, this bit is set to "1" when a parity error is generated. A parity error is
generated when the parity generated from the received data is different from the parity
received. This flag is set to "0" when it is read.
In the I/O interface mode, this bit indicates an under-run error. When the double buffer
control bit <WBUF> of the serial mode control register HSC0MOD2 is set to "1" in the
HSCLK input mode, if no data is set to the transmit double buffer before the next data
transfer clock after completing the transmission from the transmit shift register, this
error flag is set to "1" indicating an under-run error. If the transmit FIFO is enabled, any
data content in the transmit FIFO will be moved to the buffer. When the transmit FIFO
and the double buffer are both empty, an under-run error will be generated. Because
no under-run errors can be generated in the HSCLK output mode, this flag is
inoperative and the operation is undefined. If Transmit Buffer 2 is disabled, the
under-run flag <PERR> will not be set. This flag is set to "0" when it is read.
In the UART mode, this bit is set to "1" when a framing error is generated. This flag is
set to "0" when it is read. A framing error is generated if the corresponding stop bit is
determined to be "0" by sampling the bit at around the center. Regardless of the
<SBLEN> (stop bit length) setting of the serial mode control register 2, HSC0MOD2,
the stop bit status is determined by only 1 bit on the receive side.
In both UART and I/O interface modes, this bit is set to "1" when an error is generated
Operation mode
UART
(HSCLK input)
(HSCLK output)
I/O interface
I/O interface
TMP19A61(rev 1.0)14-369
Error flag
OERR
PERR
FERR
OERR
PERR
FERR
OERR
PERR
FERR
Function
Overrun error flag
Parity error flag
Framing error flag
Overrun error flag
Underrun error flag(WBUF ＝ 1)
Fixed to 0(WBUF ＝ 0)
Fixed to 0
Operation undefined
Operation undefined
Fixed to 0
TMP19A61