tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 94

• Manufacturer Part Number: tmp19a61f10xbg
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

6.12.2
Cautions Related to INTC
・ If more than one interrupts of a same interrupt level are generated at the same time,
・ Any factor of interrupt level 0 is not suspended.
・ If it is desired to individually disable interrupt factors (by setting interrupt level 0), you can
・ Default settings of IMCx <EIMxx> of INTC may be different from the settings to be used.
・ The INTC ILEV register must be 32-bit accessed.
・ The INTC INTCLR register must be 32-bit accessed.
・ When enabling interrupts, be sure to do so in the order of the detection route (from
・ When a new value is written to INTC ILEV <CMASK>, set <MLEV> to "1" at the same
interrupts are accepted from the factor of the smallest interrupt number.
do so only while interrupts are disabled.
external to internal). When disabling, use the reverse order of the detection route (from
internal to external).
time.
TMP19A61(rev1.0)-6-93
TMP19A61