tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 261

• Manufacturer Part Number: tmp19a61f10xbg
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

DREQFLG
(0xFFFF_E064)
10.5 DREQFLG Register
bit
Symbol
Read/
Write
After
reset
(Note) If a DMAC transfer request is cleared by DREQFLG in level detection,
Function
19A61 newly adds the DREQFLG register that can monitor and clear DMAC transfer request.
When reading: “0” With DREQ input
When writing: “1” Clears DREQ.
Writing “1” to the DREQFLG register can clear a DMAC transfer request.
another DMAC transfer request is generated in the next clock, as is the
case with INTCLR.
To avoid another DMAC transfer request, set the interrupt level inactive
before clearing DREQ or clear the dmdata bit of the IMC register (inactivate
DMAC) .
R/W
DREQC
h7
7
1
“1” No DREQ input (default setting after reset)
“0” Data invalid
DREQC
R/W
h6
6
1
TMP19A61 (rev1.0)10-260
DREQCh
R/W
5
5
1
DREQ monitoring/ clearing control
DREQCh4 DREQC
0: With DREQ input
1: No DREQ input
0: Data invalid
1: Clears DREQ
R/W
4
1
When reading
When writing
R/W
h3
3
1
DREQCh
R/W
2
2
1
DREQCh
R/W
1
1
1
TMP19A61
DREQCh0
R/W
0
1