tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 194

• Manufacturer Part Number: tmp19a61f10xbg
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

8. External Bus Interface
The TMP19A61 has a built-in external bus interface function to connect to external memory, I/Os,
etc. This interface consists of an external bus interface circuit (EBIF), a chip selector (CS) and a
wait controller.
The chip selector and wait controller designate mapping addresses in a 6-block address space and
also control wait states and data bus widths (8- or 16-bit) in these and other external address
spaces.
The external bus interface circuit (EBIF) controls the timing of external buses based on the chip
selector and wait controller settings. The EBIF also controls the dynamic bus sizing and the bus
arbitration with the external bus master.
• External bus mode
• Wait function
( Data bus width
( Recovery cycle (read/write)
( Recovery cycle (chip selector)
• Bus arbitration function
This function can be enabled for each block.
Either an 8- or 16-bit width can be set for each block.
If external bus cycles occur continuously, a dummy cycle of up to 4 clocks can be inserted and
this dummy cycle can be specified for each block.
When an external bus is selected, a dummy cycle of up to 31 clocks can be inserted and this
dummy cycle can be specified for each block.
Selectable address, data separator bus mode and multiplex mode
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•
A wait of up to 15 clocks can be automatically inserted.
A wait can be inserted via the WAIT / RDY pin.
TMP19A61(rev1.0)-8-193
TMP19A61