tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 234

• Manufacturer Part Number: tmp19a61f10xbg
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

( Note) In Fig. 10.1, signals indicated by * are internal signals.
10.2 Configuration
10.2.1 Internal Connections of the TMP19A61
he DMAC has eight DMA channels. Each of these channels handles the data transfer request signal
( INTDREQn ) from the interrupt controller and the acknowledgment signal ( DACKn ) generated in
response to INTDREQn ("n" is a channel number from 0 to 7). External pins (
are internally wired to allow them to function as pin of the port Q. To use them as a pin of the port Q, they
must be selected by setting the function control register PQFC to an appropriate setting.
Pins handle the data transfer request from external pins
output supplied through external pins,
channel 1. Channel 1 is given higher priority than channel 2. Channel 2 is given higher priority than
channel 3. Subsequent channels are given priority in the same manner.
The TX19A processor core has a snoop function. Using the snoop function, the TX19A processor core
opens the core's data bus to the DMAC, thus allowing the DMAC to access the internal ROM and RAM
linked to the core. The DMAC is capable of determining whether or not to use this snoop function. For
further information on the snoop function, refer to 10.2.3 “Snoop Function”.
In the DMAC, bus control authority can be select from SREQ and GREQ depend on the use or nonuse
of the snoop function. GREQ is a request for bus control authority if the DMAC does not use the snoop
function, while SREQ is a request for bus control authority if the DMAC uses the snoop function. SREQ
Fig. 10.1 shows the internal connections with the DMAC in the TMP19A61.
Notification of bus control
Notification to release
bus control authority
Request for bus control
Request to release bus
Processor core
authority ownership
TX19A
control authority
Address
Control
Data
Fig. 10.1 DMAC Connections in the TMP19A61
DREQ [2,3]
TMP19A61 (rev1.0)10-233
Port function
control
DACK
DACK [2,3]
DMAC
3
INTDREQ [7 : 0] *
and
DACK [7 : 0] *
DACK . Channel 0 is given higher priority than
DREQ
2
BUSGNT
3
(External request)
and
controller
Interrupt
*
DREQ
2
and acknowledge signal
TMP19A61
DREQ
3
External
interrupt request
Internal I/O
interrupt request
BUSREL *
BUSREQ *
HAVEIT *
and
DREQ )
2