tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 410

• Manufacturer Part Number: tmp19a61f10xbg
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Example:
direction bit is "1" in the slave receiver mode
INTSBI interrupt
Slave mode (<MST> = "0")
In the slave mode, the SBI generates the INTSBI interrupt request on four occasions: 1)
when the SBI has received any slave address from the master, 2) when the SBI has
received a general-call address, 3) when the received slave address matches its own
address, and 4) when a data transfer has been completed in response to a general-call.
Also, if the SBI loses arbitration in the master mode, it switches to the slave mode. Upon
the completion of data word transfer in which arbitration is lost, the INTSBI interrupt
request is generated, <PIN> is cleared to "0," and the SCL pin is pulled to the "L" level.
When data is written to or read from SBI0DBR or when <PIN> is set to "1," the SCL pin is
released after a period of t
In the slave mode, the normal slave mode processing or the processing as a result of lost
arbitration is carried out.
SBISR <AL>, <TRX>, <AAS> and <AD0> are tested to determine the processing required.
Table 15.6.3.4 shows the slave mode states and required processing.
(Note)
If TRX = 0
Then go to other processing
If AL = 1
Then go to other processing
If AAS = 0
Then go to other processing
SBI0CR1 ← X X X 1 0 X X X
SBI0DBR ← X X X X 0 X X X
When the received slave address matches the SBI's own address and the
TMP19A61
X: Don’t care
LOW
.
(
rev1.0
Sets the number of bits to be transmitted.
Sets the transmit data.
)
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TMP19A61