tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 9

• Manufacturer Part Number: tmp19a61f10xbg
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Pin name
P00~P07
D0~D7
AD0~D7
P10~P17
D8~D15
AD8~AD15
A8~A15
P20~P27
A16~A23
A0~A7
A16~A23
P30
*RD
P31
*WR
P32
*HWR
P33
*WAIT
*RDY
P34
*BUSRQ
P35
*BUSAK
P36
R/*W
P37
ALE
P40
*CS0
P41
*CS1
P42
*CS2
P43
*CS3
P44
*CS4
P45
*CS5
P46
SCOUT
P47
2.3
Tables 2.3 show the names and functions of input and output pins.
Pin Names and Functions
# of
pins
8
8
8
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Input
or
output
I/O
I/O
I/O
I/O
I/O
I/O
O
I/O
O
O
O
I/O
O
I/O
O
I/O
O
I/O
I
I
I/O
I
I/O
O
I/O
O
I/O
O
I/O
O
I/O
O
I/O
O
I/O
O
I/O
O
I/O
O
I/O
O
I/O
Port 47: Input/output port
PU: Programmable pull-up
Port 0: Input/output port that allows input/output to be set in units
of bits
Data (lower): Data bus 0~7 (separate bus mode)
Address data (lower): Address data bus 0~7 (multiplexed bus
mode)
Port 1: Input/output port that allows input/output to be set in units
of bits
Data (upper): Data bus 8~15: (separate bus mode)
Address data (upper): Address data bus 8~15 (multiplexed bus
mode)
Address: Address bus 8~15 (multiplexed bus mode)
Port 2: Input/output port that allows input/output to be set in units
of bits
Address: Address bus 16~23 (separate bus mode)
Address: Address bus 0~7 (multiplexed bus mode)
Address: Address bus 16~23 (multiplexed bus mode)
Port 30:Input/output port
Read: Strobe signal for reading external memory
Port 31:Input/output port
Write: Strobe signal for writing data of D0 to D7 pins
Port 32:Input/output port
Write upper-pin data: Strobe signal for writing data of D8 to D15
pins
Port 33:Input/output port
Wait: Pin for requesting CPU to put a bus in a wait state
Ready: Pin for notifying CPU that a bus is ready
Port 34:Input/output port
Bus request: Signal requesting CPU to allow an external master
to take the bus control authority
Port 35:Input/output port
Bus acknowledge: Signal notifying that CPU has released the
bus control authority in response to *BUSREQ
Port 36:Input/output port
Read/write: "1" shows a read cycle or a dummy cycle. "0" shows
a write cycle.
Port 37:: Input/output port
Address latch enable (address latch is enabled only if access to
external memory is taking place, that is multiplex bus mode)
Port 40:Input/output port
Chip select 0:”0” is output if the address is in a designated
address area.
Port 41:Input/output port
Chip select 1:”0” is output if the address is in a designated
address area.
Port 42:Input/output port
Chip select 2:”0” is output if the address is in a designated
address area.
Port 43:Input/output port
Chip select 3:”0” is output if the address is in a designated
address area.
Port 44:Input/output port
Chip select 4:”0” is output if the address is in a designated
address area.
Port 45:Input/output port
Chip select 5:”0” is output if the address is in a designated
address area.
Port 46: Input/output port
System clock output: Selectable between high- and low-speed
clock outputs, as in the case of CPU
Table 2.3 Pin Names and Functions ( 1/10)
TMP19A61 (rev1.0)2-8
Function
PU/P
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
D
TMP19A61
Schmitt
Open
Drain
PS