tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 362

• Manufacturer Part Number: tmp19a61f10xbg
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

The CPU will read the data from either Receive Buffer 2 (HSC0BUF) or from the receive
FIFO (the address is the same as that of the receive buffer). If the receive FIFO has not
been enabled, the receive buffer full flag <RBFLL> is cleared to "0" by the read operation.
The next data received can be stored in Receive Buffer 1 even if the CPU has not read the
previous data from Receive Buffer 2 (HSC0BUF) or the receive FIFO.
If HSCLK is set to generate clock output in the I/O interface mode, the double buffer control
bit HSC0MOD2 <WBUF> can be programmed to enable or disable the operation of
Receive Buffer 2 (HSCOBUF).
By disabling Receive Buffer 2 and also disabling the receive FIFO (HSCOFCNF <CNFG> =
0 and <FDPX1:0> = 01), handshaking with the other side of communication can be enabled
and the HSCLK output stops each time one frame of data is transferred. In this setting, the
CPU reads data from Receive Buffer 1. By the read operation of CPU, the HSCLK output
resumes.
If the Receive Buffer 2 (i.e., double buffering) is enabled but the receive FIFO is not enabled,
the HSCLK output is stopped when the first receive data is moved from Receive Buffer 1 to
Receive Buffer 2 and the next data is stored in the first buffer filling both buffers with valid
data. When Receive Buffer 2 is read, the data of Receive Buffer 1 is moved to Receive
Buffer 2 and the HSCLK output is resumed upon generation of the receive interrupt
HINTRX. Therefore, no buffer overrun error will be caused in the I/O interface HSCLK
output mode regardless of the setting of the double buffer control bit HSC0MOD2 <WBUF>.
If Receive Buffer 2 (double buffering) is enabled and the receive FIFO is also enabled
(HSCNFCNF<CNFG>=1 and HSC0MOD1<FDPX1:0> ＝ 01/11), the HSCLK output will be
stopped when the receive FIFO is full (according to the setting of HSCOFNCF<RFST>) and
both Receive Buffers 1 and 2 contain valid data. Also in this case, if
HSC0FCNF<RXTXCNT> has been set to "1," the receive control bit RXE will be
automatically cleared upon suspension of the HSCLK output. If it is set to "0," automatic
clearing will not be performed.
In other operating modes, the operation of Receive Buffer 2 is always valid, and it enables
to improve the performance of continuous data transfer. If the receive FIFO is not enabled,
an overrun error occurs when the data in Receive Buffer 2 (HSC0BUF) has not been read
before Receive Buffer 1 is full with the next receive data. If an overrun error occurs, data in
Receive Buffer 1 will be lost while data in Receive Buffer 2 and the contents of HSC0CR
<RB8> remain intact. If the receive FIFO is enabled, the FIFO must be read before the FIFO
is full and Receive Buffer 2 is written by the next data through the first buffer. Otherwise, an
overrun error will be generated and the receive FIFO overrun error flag will be set. Even in
this case, the data already in the receive FIFO remains intact.
9-bit UART mode will be stored in HSC0CR <RB8>.
setting the wake-up function HSC0MOD0 <WU> to "1." In this case, the interrupt HINTRX0
will be generated only when HSC0CR <RB8> is set to "1."
The parity bit to be added in the 8-bit UART mode as well as the most significant bit in the
In the 9-bit UART mode, the slave controller can be operated in the wake-up mode by
(Note) In this mode, the HSC0CR <OERR> flag is insignificant and the operation
is undefined. Therefore, before switching from the HSCLK output mode
to another mode, the HSC0CR register must be read to initialize this flag.
TMP19A61(rev 1.0)14-361
TMP19A61