tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 332

• Manufacturer Part Number: tmp19a61f10xbg
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

13.3.16 Direction of Data Transfer
13.3.17 Stop Bit Length
13.3.18 Status Flag
13.3.19 Configurations of Transmit/Receive Buffers
In the I/O interface mode, the direction of data transfer can be switched between "MSB first"
and "LSB first" by the data transfer direction setting bit <DRCHG> of the SC0MOD2 serial
mode control register 2. Don't switch the direction when data is being transferred.
In the UART mode transmission, the stop bit length can be set to either 1 or 2 bits by bit 4
<SBLEN> of the SC0MOD2 register.
If the double buffer function is enabled (SC0MOD2 <WBUF> = "1"), the bit 6 flag <RBFLL>
of the SC0MOD2 register indicates the condition of receive buffer full. When one frame of
data has been received and transferred from buffer 1 to buffer 2, this bit is set to "1" to show
that buffer 2 is full (data is stored in buffer 2). When the receive buffer is read by
CPU/DMAC, it is cleared to "0." If <WBUF> is set to "0," this bit is insignificant and must not
be used as a status flag.
When double buffering is enabled (SC0MOD2 <WBUF> = "1"), the bit 7 flag <TBEMP> of
the SC0MOD2 register indicates that transmit buffer 2 is empty. When data is moved from
transmit buffer 2 to transmit buffer 1 (shift register), this bit is set to "1" indicating that
transmit buffer 2 is now empty. When data is set to the transmit buffer by CPU/DMAC, the
bit is cleared to "0." If <WBUF> is set to "0," this bit is insignificant and must not be used as
a status flag.
(SCLK output)
(SCLK input)
I/O interface
I/O interface
UART
TMP19A61 (rev1.0)-13-331
Transmit buffer
Transmit buffer
Transmit buffer
Receive buffer
Receive buffer
Receive buffer
<WBUF> = 0
Double
Double
Single
Single
Single
Single
<WBUF> = 1
Double
Double
Double
Double
Double
Double
TMP19A61