tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 281

• Manufacturer Part Number: tmp19a61f10xbg
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

TBnRUN
(0xFFFF_F2x0)
TB0CRUN
(0xFFFF_F2C0)
<TBnRUN>: Controls the TMRBn count operation.
<TBnPRUN>:Controls the TMRBn prescaler operation.
<I2TBn>:Controls the operation in the IDLE mode.
<TBnWBUF>:Controls enabling/disabling of double buffering.
<TB0CRUN>:Controls the TMRB0C count operation.
<TB0CPRUN>:Controls the TMRB0C prescaler operation.
<I2TBA>:Controls the operation in the IDLE mode.
<TB0CUDCE>:Controls enabling/disabling of the two-phase pulse input count operation.
<UD0CCK>:Selects the two-phase pulse input sampling clock.
<TB0CRDE>:Controls enabling/disabling of double buffering.
11.3 Register Description
Bit symbol
Read/Write
After reset
Bit symbol
Read/Write
After reset
Function
Function
Enable: The counter counts up and counts down.
Disable: This is the normal timer mode and the counter counts up only.
Double
Buffer
0: Disable
1: Enable
Double
Buffer
0: Disable
1: Enable
TBnWBUF
TB0CRDE
R/W
R/W
7
7
0
0
TMRBn RUN register (n=00 ~ 23, except for 0C and 12)
Write “0”.
Write “0”.
R/W
R/W
6
6
0
0
TMP19A61 (rev 1.0)11-280
Sampling
clock
0:
1: ΦT0/4
Write “0”.
UDACK
TMRB0C RUN register
R/W
R/W
5
5
0
0
disable
two-phase
counter
0: Disable
1: Enable
Write “0”.
TB0CUDC
Enable/
R/W
R/W
4
4
E
0
0
IDLE
0: Stop
1: Operation
IDLE
0: Stop
1: Operation
I2TBn
I2TBA
R/W
R/W
3
3
0
0
Timer Run/Stop Control
0: Stop & clear
1: Count
* The first bit can be read as “0.”
Timer Run/Stop Control
0: Stop & clear
1: Count
* The first bit can be read as “0.”
TBnPRUN
TB0CPRU
R/W
R/W
2
2
N
0
0
1
R
1
R
0
0
TMP19A61
TB0CRUN
TBnRUN
R/W
R/W
0
0
0
0