tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 242

• Manufacturer Part Number: tmp19a61f10xbg
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Bit
31
24
23
22
21
20
19
18
17
16
15
14
13
12
11
Mnemonic
AbIEn
SReq
PosE
NIEn
ExR
Lev
Big
Str
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Channel start
(Reserved)
Normal
interrupt enable
Abnormal
interrupt enable
(Reserved)
(Reserved)
(Reserved)
(Reserved)
Big-endian
(Reserved)
(Reserved)
External request mode
Positive edge
Level mode
Snoop request
Field name
completion
completion
TMP19A61 (rev1.0)10-241
Start (initial value:–)
Starts channel operation. If this bit is set to 1, the channel goes into
a standby mode and starts to transfer data in response to a transfer
request.
Only a write of 1 is valid to the Str bit and a write of 0 is ignored. A
read always returns 0.
1: Starts channel operation
This is a reserved bit. Always set this bit to "0."
Normal Completion Interrupt Enable (initial value: 1)
1: Normal completion interrupt enable
0: Normal completion interrupt disable
Abnormal Completion Interrupt Enable (initial value:1)
1: Abnormal completion interrupt enable
0: Abnormal completion interrupt disable
This is a reserved bit. Although it’s initial value is "1," always set this
bit to “0”.
This is a reserved bit. Always set this bit to "0."
This is a reserved bit. Always set this bit to "0."
This is a reserved bit. Always set this bit to "0."
Big Endian (initial value: 1)
1: A channel operates by big-endian
0: A channel operates by little-endian
This is a reserved bit. Always set this bit to "0."
This is a reserved bit. Always set this bit to "0."
External Request Mode (initial value: 0)
Selects a transfer request mode. (only for 2ch and 3ch)
1: External transfer request (interrupt request or external DREQn
request)
0: Internal transfer request (software initiated)
Positive Edge (initial value: 0)
The effective level of the transfer request signal INTDREQn or
DREQn is specified. This function is valid only if the transfer request
is an external transfer request (if the ExR bit is 1). If it is an internal
transfer request (if the ExR bit is 0), the PosE value is ignored.
Because the INTDREQn and DREQn signals are active at "L" level,
make sure that this PosE bit is set to "0."
1: Setting prohibited
Level Mode (initial value: 0)
Specifies signal level or signal change for recognizing the external
transfer request. This setting is valid only if a transfer request is the
external transfer request (if the ExR bit is 1). If the internal transfer
request is specified as a transfer request (if the ExR bit is 0), the
value of the Lev bit is ignored. Because the INTDREQn signal is
active at "L" level, make sure that you set the Lev bit to "1." The state
of active DREQn is determined by the Lev bit setting.
1: Level mode
0: Edge mode
Snoop Request (initial value: 0)
The use of the snoop function is specified by asserting the bus
control request mode. If the snoop function is used, the snoop
function of the TX19A processor core is enabled and the DMAC can
use the data bus of the TX19A processor core. If the snoop function
is not used, the snoop function of the TX19A processor core does
not work.
1: Use snoop function (SREQ)
0: Do not use snoop function (GREQ)
The level of the DREQn signal is recognized as a data transfer
request. (The "L" level is recognized if the PosE bit is 0.)
A change in the DREQn signal is recognized as a data transfer
request. (A falling edge is recognized if the PosE bit is 0.)
0: The falling edge of the INTDREQn or DREQn signal or the "L"
level is effective. The DACKn is active at "L" level.
Description
TMP19A61