tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 236

• Manufacturer Part Number: tmp19a61f10xbg
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

10.3 Registers
The DMAC has fifty-one 32-bit registers. Table 10.1 shows the register map of the DMAC.
0xFFFF_E200
0xFFFF_E204
0xFFFF_E208
0xFFFF_E20C
0xFFFF_E210
0xFFFF_E218
0xFFFF_E220
0xFFFF_E224
0xFFFF_E228
0xFFFF_E22C
0xFFFF_E230
0xFFFF_E238
0xFFFF_E240
0xFFFF_E244
0xFFFF_E248
0xFFFF_E24C
0xFFFF_E250
0xFFFF_E258
0xFFFF_E260
0xFFFF_E264
0xFFFF_E268
0xFFFF_E26C
0xFFFF_E270
0xFFFF_E278
0xFFFF_E280
0xFFFF_E284
0xFFFF_E288
0xFFFF_E28C
0xFFFF_E290
0xFFFF_E298
0xFFFF_E2A0
0xFFFF_E2A4
0xFFFF_E2A8
0xFFFF_E2AC
0xFFFF_E2B0
0xFFFF_E2B8
Address
Register symbol
DTCR0
DTCR1
DTCR2
DTCR3
DTCR4
DTCR5
CCR5
CCR0
CSR0
SAR0
DAR0
BCR0
CCR1
CSR1
SAR1
DAR1
BCR1
CCR2
CSR2
SAR2
DAR2
BCR2
CCR3
CSR3
SAR3
DAR3
BCR3
CCR4
CSR4
SAR4
DAR4
BCR4
CSR5
SAR5
DAR5
BCR5
Table 10.1 DMAC Registers 1
TMP19A61 (rev1.0)10-235
Channel control register (ch. 0)
Channel status register (ch. 0)
Source address register (ch. 0)
Destination address register (ch. 0)
Byte count register (ch. 0)
DMA transfer control register (ch. 0)
Channel control register (ch. 1)
Channel status register (ch. 1)
Source address register (ch. 1)
Destination address register (ch. 1)
Byte count register (ch. 1)
DMA transfer control register (ch. 1)
Channel control register (ch. 2)
Channel status register (ch. 2)
Source address register (ch. 2)
Destination address register (ch. 2)
Byte count register (ch. 2)
DMA transfer control register (ch. 2)
Channel control register (ch. 3)
Channel status register (ch. 3)
Source address register (ch. 3)
Destination address register (ch. 3)
Byte count register (ch. 3)
DMA transfer control register (ch. 3)
Channel control register (ch. 4)
Channel status register (ch. 4)
Source address register (ch. 4)
Destination address register (ch. 4)
Byte count register (ch. 4)
DMA transfer control register (ch. 4)
Channel control register (ch. 5)
Channel status register (ch. 5)
Source address register (ch. 5)
Destination address register (ch. 5)
Byte count register (ch. 5)
DMA transfer control register (ch. 5)
Register name
TMP19A61