tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 297

• Manufacturer Part Number: tmp19a61f10xbg
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

TB0CRUN
(0xFFFF_F2C0)
TB0CST
(0xFFFF_F1E4)
Bit symbol
Read/Write
After reset
Function
Bit symbol
Read/Write
After reset
Function
•
The INTTB0C interrupt is enabled using the interrupt controller (INTC). The INTTB0C
interrupt is generated by counting up or down. Reading the status register TB0CST during
interrupt handling allows simultaneous check for occurrences of an overflow and an
underflow. If TB0CST<INTTBOUFC> is “1,” it indicates that an overflow has occurred. If
<INTTBUDF0C> is “1,” it indicates that an underflow has occurred. This register is cleared
after it is read. The counter becomes 0x0000 when an overflow occurs, and it becomes
0xFFFF when an underflow occurs.
operation.
Interrupt
Double
Buffer
0: Disable
1: Enable
Set the 5
This can be read as “0”.
TB0CRD
Fig. 11.4.6.1 Two-phase Pulse Input Count Mode Setting Register
In the NORMAL mode
R/W
(Note) The status is cleared after the register is read.
7
E
0
7
th
Write “0”.
bit of TB0CRUN register <UDCCK> to “1” as a sampling clock.
R/W
6
0
6
R
0
Fig. 11.4.6.2 TMRB0C status register
TMR0C RUN register (TB0CRUN)
TMP19A61 (rev 1.0)11-296
Sampling
clock
selection
1:φT0/4
UD0CCK
R/W
5
0
5
disable
two-phase
counter
0: Disable
1: Enable
Enable/
TB0CUDC
Up-and-dow
n count
0: Not
1: Occurred
INTTBUD0
occurred
R/W
4
E
0
4
C
0
After that, the counter continues the counting
IDLE
0: Stop
1:
Operation
INTTBUDF0
Underflow
0: Not
1: Occurred
I2TB0C
occurred
R/W
3
0
3
R
C
0
Timer Run/Stop Control
0: Stop & Clear
1: Run (Count Up)
TB0CPRU
INTTBOUF0
Overflow
0: Not
1: Occurred
occurred
R/W
N
2
0
2
C
0
This can be read as “0”.
1
R
0
1
TMP19A61
R
0
TB0CRU
R/W
0
N
0
0