tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 239

• Manufacturer Part Number: tmp19a61f10xbg
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Bit
31
7
6
5
4
3
2
1
0
Mnemonic
Rstall
Rst7
Rst6
Rst5
Rst4
Rst3
Rst2
Rst1
Rst0
Reset all
Reset 7
Reset 6
Reset 5
Reset 4
Reset 3
Reset 2
Reset 1
Reset 0
Field name
Fig. 10.3 DMA Control Register (DCR)
TMP19A61 (rev1.0)10-238
Performs a software reset of the DMAC. If the Rstall bit is set to 1, the values of all the
internal registers of the DMAC are reset to their initial values. All transfer requests are
canceled and all four channels go into an idle state.
0: Don't care
1: Initializes the DMAC
Performs a software reset of the DMAC channel 7. If the Rst7 bit is set to 1, internal
registers of the DMAC channel 7 and a corresponding bit of the channel 7 of the RSR
register are reset to their initial values. The transfer request of the channel 7 is
canceled and the channel 7 goes into an idle state.
0: Don't care
1: Initializes the DMAC channel 7
Performs a software reset of the DMAC channel 6. If the Rst6 bit is set to 1, internal
registers of the DMAC channel 6 and a corresponding bit of the channel 6 of the RSR
register are reset to their initial values. The transfer request of the channel 6 is
canceled and the channel 6 goes into an idle state.
0: Don't care
1: Initializes the DMAC channel 6
Performs a software reset of the DMAC channel 5. If the Rst2 bit is set to 1, internal
registers of the DMAC channel 5 and a corresponding bit of the channel 5 of the RSR
register are reset to their initial values. The transfer request of the channel 5 is
canceled and the channel 5 goes into an idle state.
0: Don't care
1: Initializes the DMAC channel 5
Performs a software reset of the DMAC channel 4. If the Rst2 bit is set to 1, internal
registers of the DMAC channel 4 and a corresponding bit of the channel 4 of the RSR
register are reset to their initial values. The transfer request of the channel 4 is
canceled and the channel 4 goes into an idle state.
0: Don't care
1: Initializes the DMAC channel 4
Performs a software reset of the DMAC channel 3. If the Rst2 bit is set to 1, internal
registers of the DMAC channel 3 and a corresponding bit of the channel 3 of the RSR
register are reset to their initial values. The transfer request of the channel 3 is
canceled and the channel 3 goes into an idle state.
0: Don't care
1: Initializes the DMAC channel 3
Performs a software reset of the DMAC channel 2. If the Rst2 bit is set to 1, internal
registers of the DMAC channel 2 and a corresponding bit of the channel 2 of the RSR
register are reset to their initial values. The transfer request of the channel 2 is
canceled and the channel 2 goes into an idle state.
0: Don't care
1: Initializes the DMAC channel 2
Performs a software reset of the DMAC channel 1. If the Rst2 bit is set to 1, internal
registers of the DMAC channel 1 and a corresponding bit of the channel 1 of the RSR
register are reset to their initial values. The transfer request of the channel 1 is
canceled and the channel 1 goes into an idle state.
0: Don't care
1: Initializes the DMAC channel 1
Performs a software reset of the DMAC channel 0. If the Rst2 bit is set to 1, internal
registers of the DMAC channel 0 and a corresponding bit of the channel 0 of the RSR
register are reset to their initial values. The transfer request of the channel 0 is
canceled and the channel 0 goes into an idle state.
0: Don't care
1: Initializes the DMAC channel 2
Description
TMP19A61