tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 371

• Manufacturer Part Number: tmp19a61f10xbg
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

14.1.19 Software Reset
14.1.15 Direction of Data Transfer
14.1.16 Stop Bit Length
14.1.17 Status Flag
14.1.18 Configurations of Transmit/Receive Buffers
and "LSB first" by the data transfer direction setting bit <DRCHG> of the HSC0MOD2 serial
mode control register 2. Don't switch the direction when data is being transferred.
In the UART mode transmission, the stop bit length can be set to either 1 or 2 bits by bit 4
<SBLEN> of the HSC0MOD2 register.
<RBFLL> of the HSC0MOD2 register indicates the condition of receive buffer full. When
one frame of data has been received and transferred from buffer 1 to buffer 2, this bit is set
to "1" to show that buffer 2 is full (data is stored in buffer 2). When the receive buffer is read
by CPU/DMAC, it is cleared to "0." If <WBUF> is set to "0," this bit is insignificant and must
not be used as a status flag. When double buffering is enabled (HSC0MOD2 <WBUF> =
"1"), the bit 7 flag <TBEMP> of the HSC0MOD2 register indicates that transmit buffer 2 is
empty. When data is moved from Transmit Buffer 2 to Transmit Buffer 1 (shift register), this
bit is set to "1" indicating that Transmit Buffer 2 is now empty. When data is set to the
transmit buffer by CPU/DMAC, the bit is cleared to "0." If <WBUF> is set to "0," this bit is
insignificant and must not be used as a status flag.
In the I/O interface mode, the direction of data transfer can be switched between "MSB first"
If the double buffer function is enabled (HSC0MOD2 <WBUF> = "1"), the bit 6 flag
“10”
HSC0MOD1<TXE> ， HSC0MOD2<TBEMP>,<RBFLL>,<TXRUN>, control registers
HSC0CR<OERR>, <PERR>, <FERR> and their internal circuits are initialized. Other
conditions are intact.
Software reset is generated by writing bit 1, 0 <SWRST1:0> of HSC0MOD2 register as
(HSCLK output)
(HSCLK input)
I/O interface
I/O interface
followed
UART
by
TMP19A61(rev. 1.0) 14-370
“01”.
Transmit
Transmit
Transmit
Receive
Receive
Receive
buffer
buffer
buffer
buffer
buffer
buffer
As
a
result,
WBUF = 0
Double
Double
Single
Single
Single
Single
mode
registers
WBUF = 1
Double
Double
Double
Double
Double
Double
TMP19A61
HSC0MOD0<RXE>,