tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 556

• Manufacturer Part Number: tmp19a61f10xbg
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

［2］Multiplex bus mode
(Note)
No. 1 to 21:
AC measurement conditions:
No.
10
11
12
13
14
15
16
17
18
19
20
21
1
2 A0-15 valid to ALE low
3 A0-15 hold after ALE low
4 ALE pulse width high
5
6
7
8
9
Internal 2 wait insertion, ALE “1” Clock, @54MHz
TW = W + 2N,
ALE=ALE output width
TW = 2 + 2*1 = 4
Output levels:
Input levels: High = 0.7DVCC33 V/Low 0.3DVCC33 V
1) ALE=1 clock cycle, 2 programmed wait state
System clock period (x)
asserted
high
A0-15 valid to RD / WR or HWR
asserted
A16-23 valid to RD / WR or HWR
asserted
A16-23 hold after RD / WR or HWR
negated
A0-15 valid to D0-15 data in
A16-23 valid to D0-15 data in
D0-15 hold after RD negated
D0-15 valid to WR or HWR negated
D0-15 hold after WR or HWR negated
A16-23 valid to WAIT input
A0-15 valid to WAIT input
(1) DVCC15=CVCC15=1.35V~1.65V, DVCC3n=2.3V~3.3V
RD asserted to D0-15 data in
RD pulse width low
RD negated to next A0-15 output
ALE low to RD / WR or HWR
WR / HWR pulse width low
WAIT hold after RD / WR or HWR
RD / WR or HWR negated to ALE
Parameter
High = 0.8DVCC33 V/Low 0.2DVCC33 V, CL = 30 pF
TMP19A61 (rev 1.0)-24-555
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
WW
WD
SYS
AL
LA
LL
LC
CL
ACL
ACH
CAR
ADL
ADH
RD
RR
HR
RAE
DW
AWH
AWL
CW
x(1+W)-10
x(1+W)-10
x(1+W)-18
(ALE)x-12
x(TW-3)-1
(ALE)x-6
2x-20
2x-20
Min
18.5
x-15
x-14
x-15
x-15
x-8
x-8
0
Equation
x+(ALE)x+(W-1)x
x+(ALE)x+(W-1)x
x(2+W+ALE)-42
x(2+W+ALE)-42
x(TW-1)-30
x(1+W)-28
Max
-30
-30
TMP19A61
Min
18.5
10.5
12.5
10.5
17.0
17.0
45.5
45.5
37.5
17.5
6.5
3.5
4.5
3.5
3.5
54 MHz
0
(fsys)
Max
50.5
50.5
27.5
25.5
25.5
25.5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns