tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 528

• Manufacturer Part Number: tmp19a61f10xbg
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Chip
Area to select
0
1
As for the addresses from the first to the sixth bus cycles, specify the upper 4 bit
with the corresponding flash memory addresses of the blocks to be erased.
Example: When BA0 is to be selected, any single address in the range 0xBFC0_0000 to
Table 22.12 The ID-Read command's fourth bus write cycle ID address (IA) and
0xBFC1_FFFF may be entered.
Block 0
Block 1
Block 2
Block 3
Block 4
Block 5
Block 6
Block 7
OPBA
OPBA
Block 0
Block 1
Block 2
Block 3
Block 0
Block 1
Block 2
Block 3
BA
The protection bit erase command will erase bits 0 and 1 together.
The bits 2 and 3 are also erased together.
0
0
0
0
1
1
1
1
[19]
configuration
the data to be read by the following LW command (ID)
Table 22.10 Protection Bit Programming Address Table
Address
0
0
1
1
0
0
1
1
[18]
IA [15:14]
Table 22. 9 Block Erase Address Table
0
1
0
1
0
1
0
1
[17]
00b
01b
10b
11b
Address [15]
Address [15]
The seventh bus write cycle address [15:14]
The seventh bus write cycle address [15:14]
TMP19A61 (rev1.0) 22-527
Table 22.11 Protection Bit Erase Address Table
0xBFC0_0000 ∼ 0xBFC1_F
FFF
0xBFC2_0000 ∼ 0xBFC3_F
FFF
0xBFC4_0000 ∼ 0xBFC5_F
FFF
0xBFC6_0000 ∼ 0xBFC7_F
FFF
0xBFC8_0000 ∼ 0xBFC9_F
FFF
0xBFCA_0000 ∼ 0xBFCB_
FFFF
0xBFCC_0000 ∼ 0xBFCD_
FFFF
0xBFCE_0000 ∼ 0xBFCF_
FFFF
0
0
1
1
0
0
1
1
Flash Memory
Reserved
Address
ID [7: 0 ]
0x5A
0x98
0x08
Address Range
Manufacturer
Device code
Macro code
Code
code
0x000E_0000 ∼ 0x000F_FF
0x0000_0000 ∼ 0x0001_FF
0x0002_0000 ∼ 0x0003_FF
0x0004_0000 ∼ 0x0005_FF
0x0006_0000 ∼ 0x0007_FF
0x0008_0000 ∼ 0x0009_FF
---
0x000C_0000 ∼ 0x000D_F
0x000A_0000 ∼ 0x000B_F
When applied to the
projected area
Address [14]
Address [14]
FFF
FFF
FF
FF
FF
FF
FF
FF
X
X
X
X
0
1
0
1
TMP19A61
128 KB
128 KB
128 KB
128 KB
128 KB
128 KB
128 KB
128 KB
Size