NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 847

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Electrical Characteristics
Intel
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ICH8 Family Datasheet
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The associated 3.3 V and 1.05 V supplies are assumed to power up or down ‘together’. If
the integrated VccSus1_05 voltage regulator is not used: a) VccSus3_3 must power up
before VccSus1_05 or after VccSus1_05 within 0.7 V, b) VccSus1_05 must power down
before VccSus3_3 or after VccSus3_3 within 0.7 V.
The VccSus supplies must never be active while the VccRTC supply is inactive.
Vcc1_5 must power up before V_CPU_IO or after V_CPU_IO within 0.7 V, b) V_CPU_IO
must power down before Vcc1_5 or after Vcc1_5 within 0.7 V.
INIT# value determined by value of the CPU BISTEnable bit (Chipset Configuration
Register Offset 3414h: bit 2).
The associated 3.3 V and 1.05 V supplies are assumed to power up or down ‘together’. If
the integrated VccLAN1_05 voltage regulator is not used: a) VccLan3_3 must power up
before VccLan1_05 or after VccLan1_05 within 0.7 V, b) VccLan1_05 must power down
before VccLan3_3 or after VccLan3_3 within 0.7 V.
The associated 3.3 V and 1.05 V supplies are assumed to power up or down ‘together’. If
the integrated VccCL1_05 voltage regulator is not used: a) VccCL3_3 must power up
before VccCL1_05 or after VccCL1_05 within 0.7 V, b) VccCL1_05 must power down before
VccCL3_3 or after VccCL3_3 within 0.7 V.
The associated 3.3 V and 1.5 V supplies are assumed to power up or down ‘together’. If
the integrated VccCL1_5 voltage regulator is not used: a) VccCL3_3 must power up before
VccCL1_5 or after VccCL1_5 within 0.7 V, b) VccCL1_5 must power down before VccCL3_3
or after VccCL3_3 within 0.7 V.
The associated 3.3 V and 1.5 V supplies are assumed to power up or down ‘together’. If
the integrated VccSus1_5 voltage regulator is not used: a) VccSus3_3 must power up
before VccSus1_5 or after VccSus1_5 within 0.7 V, b) VccSus1_5 must power down before
VccSus3_3 or after VccSus3_3 within 0.7 V
These transitions are clocked off the internal RTC. 1 RTC clock is approximately from
28.992 µs to 32.044 µs.
“VccGLANPLL inactive" is defined for this timing to be when VccGLANPLL drops to 1.425 V
or less, as measured at the ICH8. This timing applies only to platforms using ICH8
integrated GbE LAN.
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