NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 619

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

EHCI Controller Registers (D29:F7, D26:F7)
Intel
®
ICH8 Family Datasheet
Bit
6
5
4
3
Force Port Resume — R/W.
0 = No resume (K-state) detected/driven on port. (Default)
1 = Resume detected/driven on port. Software sets this bit to a 1 to drive resume
NOTE: When the EHCI controller owns the port, the resume sequence follows the
Overcurrent Change — R/WC. The functionality of this bit is not dependent upon the
port owner. Software clears this bit by writing a 1 to it.
0 = No change. (Default)
1 = There is a change to Overcurrent Active.
Overcurrent Active — RO.
0 = This port does not have an overcurrent condition. (Default)
1 = This port currently has an overcurrent condition. This bit will automatically
Port Enable/Disable Change — R/WC. For the root hub, this bit gets set to a 1 only
when a port is disabled due to the appropriate conditions existing at the EOF2 point
(See Chapter 11 of the USB Specification for the definition of a port error). This bit is
not set due to the Disabled-to-Enabled transition, nor due to a disconnect. Software
clears this bit by writing a 1 to it.
0 = No change in status. (Default).
1 = Port enabled/disabled status has changed.
signaling. The Host controller sets this bit to a 1 if a J-to-K transition is detected
while the port is in the Suspend state. When this bit transitions to a 1 because a J-
to-K transition is detected, the Port Change Detect bit (D29:F7,
D26:F7:CAPLENGTH + 24h, bit 2) in the USB2.0_STS register is also set to a 1. If
software sets this bit to a 1, the host controller must not set the Port Change
Detect bit.
transition from 1 to 0 when the over current condition is removed. The ICH8
automatically disables the port when the overcurrent active bit is 1.
defined sequence documented in the USB Specification, Revision 2.0. The
resume signaling (Full-speed 'K') is driven on the port as long as this bit
remains a 1. Software must appropriately time the Resume and set this bit to a
0 when the appropriate amount of time has elapsed. Writing a 0 (from 1)
causes the port to return to high-speed mode (forcing the bus below the port
into a high-speed idle). This bit will remain a 1 until the port has switched to the
high-speed idle.
Description
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