NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 546

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

13.1.15
13.1.16
13.1.17
13.1.18
546
SIDPBA — SATA Index/Data Pair Base Address Register
(SATA–D31:F5)
Address Offset: 24h
Default Value:
This register is an I/O BAR allocating 16 bytes of I/O space for the I/O-mapped
registers defined in
allocated, some locations are reserved.
SVID—Subsystem Vendor Identification Register
(SATA–D31:F5)
Address Offset: 2Ch
Default Value:
Lockable:
SID—Subsystem Identification Register (SATA–D31:F5)
Address Offset: 2Eh
Default Value:
Lockable:
CAP—Capabilities Pointer Register (SATA–D31:F5)
Address Offset: 34h
Default Value:
31:16
15:0
15:0
15:4
7:0
3:1
Bit
Bit
Bit
Bit
0
Capabilities Pointer (CAP_PTR) — RO. Indicates that the first capability pointer offset is
80h. This value changes to 70h if the MAP.MV register (Dev 31:F2:90h, bits 1:0) in
configuration space indicates that the SATA function and PATA functions are combined
(values of 10b or 10b) or Sub Class Code (CC.SCC) (Dev 31:F2:0Ah) is configure as IDE
mode (value of 01).
Subsystem Vendor ID (SVID) — R/WO. Value is written by BIOS. No hardware
action taken on this value.
Subsystem ID (SID) — R/WO. Value is written by BIOS. No hardware action taken on
this value.
Reserved
Base Address (BA) — R/W. Base address of register I/O space
Reserved
Resource Type Indicator (RTE) — RO. Hardwired to 1 to indicate a request for I/O
space.
00000001h
0000h
No
0000h
No
80h
Section
–
–
–
27h
2Fh
2Dh
13.3. Note that although 16 bytes of locations are
Description
Description
Description
Description
Attribute:
Size:
Attribute:
Size:
Power Well:
Attribute:
Size:
Power Well:
Attribute:
Size:
SATA Controller Registers (D31:F5)
R/W, RO
32 bits
R/WO
16 bits
Core
R/WO
16 bits
Core
RO
8 bits
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ICH8 Family Datasheet