NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 702

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

18.1.4
702
PCISTS—PCI Status Register
(PCI Express—D28:F0/F1/F2/F3/F4/F5)
Address Offset: 06h
Default Value:
10:9
2:0
Bit
15
14
13
12
11
8
7
6
5
4
3
Detected Parity Error (DPE) — R/WC.
0 = No parity error detected.
1 = Set when the root port receives a command or data from the backbone with a
Signaled System Error (SSE) — R/WC.
0 = No system error signaled.
1 = Set when the root port signals a system error to the internal SERR# logic.
Received Master Abort (RMA) — R/WC.
0 = Root port has not received a completion with unsupported request status from the
1 = Set when the root port receives a completion with unsupported request status from
Received Target Abort (RTA) — R/WC.
0 = Root port has not received a completion with completer abort from the backbone.
1 = Set when the root port receives a completion with completer abort from the
Signaled Target Abort (STA) — R/WC.
0 = No target abort received.
1 = Set whenever the root port forwards a target abort received from the downstream
DEVSEL# Timing Status (DEV_STS) — Reserved per the PCI Express* Base
Specification.
Master Data Parity Error Detected (DPED) — R/WC.
0 = No data parity error received.
1 = Set when the root port receives a completion with a data parity error on the
Fast Back to Back Capable (FB2BC) — Reserved per the PCI Express* Base
Specification.
Reserved
66 MHz Capable — Reserved per the PCI Express* Base Specification.
Capabilities List — RO. Hardwired to 1. Indicates the presence of a capabilities list.
Interrupt Status — RO. Indicates status of Hot-Plug and power management
interrupts on the root port that result in INTx# message generation.
0 = Interrupt is deasserted.
1 = Interrupt is asserted.
This bit is not set if MSI is enabled. If MSI is not enabled, this bit is set regardless of the
state of PCICMD.Interrupt Disable bit (D28:F0/F1/F2/F3/F4/F5:04h:bit 10).
Reserved
parity error. This is set even if PCIMD.PER (D28:F0/F1/F2/F3:04, bit 6) is not set.
backbone.
the backbone.
backbone.
device onto the backbone.
backbone and PCIMD.PER (D28:F0/F1/F2/F3:04, bit 6) is set.
0010h
–
07h
Description
Attribute:
Size:
PCI Express* Configuration Registers
R/WC, RO
16 bits
Intel
®
ICH8 Family Datasheet