NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 581

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

UHCI Controllers Registers
14.2.5
14.2.6
Intel
®
ICH8 Family Datasheet
FRBASEADD—Frame List Base Address Register
I/O Offset:
Default Value:
This 32-bit register contains the beginning address of the Frame List in the system
memory. HCD loads this register prior to starting the schedule execution by the host
controller. When written, only the upper 20 bits are used. The lower 12 bits are written
as 0’s (4 KB alignment). The contents of this register are combined with the frame
number counter to enable the host controller to step through the Frame List in
sequence. The two least significant bits are always 00. This requires dword-alignment
for all list entries. This configuration supports 1024 Frame List entries.
SOFMOD—Start of Frame Modify Register
I/O Offset:
Default Value:
This 1-byte register is used to modify the value used in the generation of SOF timing on
the USB. Only the 7 least significant bits are used. When a new value is written into
these 7 bits, the SOF timing of the next frame will be adjusted. This feature can be
used to adjust out any offset from the clock source that generates the clock that drives
the SOF counter. This register can also be used to maintain real time synchronization
with the rest of the system so that all devices have the same sense of real time. Using
this register, the frame length can be adjusted across the full range required by the
USB specification. Its initial programmed value is system dependent based on the
accuracy of hardware USB clock and is initialized by system BIOS. It may be
reprogrammed by USB system software at any time. Its value will take effect from the
beginning of the next frame. This register is reset upon a host controller reset or global
reset. Software must maintain a copy of its value for reprogramming if necessary.
31:12
6:0
11:0
Bit
Bit
7
Reserved
SOF Timing Value — R/W. Guidelines for the modification of frame time are contained
in Chapter 7 of the USB Specification. The SOF cycle time (number of SOF counter clock
periods to generate a SOF frame length) is equal to 11936 + value in this field. The
default value is decimal 64 which gives a SOF cycle time of 12000. For a 12 MHz SOF
counter clock input, this produces a 1 ms Frame period. The following table indicates
what SOF Timing Value to program into this field for a certain frame period.
Base Address — R/W. These bits correspond to memory address signals [31:12],
respectively.
Reserved
Frame Length (# 12 MHz
Clocks) (decimal)
11936
11937
11999
12000
12001
12062
12063
—
—
BASE + (08h
Undefined
Base + (0Ch)
40h
–
0Bh)
SOF Timing Value (this register)
Description
Description
Attribute:
Size:
Attribute:
Size:
(decimal)
126
127
63
64
65
—
—
0
1
R/W
32 bits
R/W
8 bits
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