NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 5

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Intel
®
ICH8 Family Datasheet
5.6
5.7
5.8
5.9
5.10
5.5.5
LPC DMA ........................................................................................................ 132
5.6.1
5.6.2
5.6.3
5.6.4
5.6.5
5.6.6
5.6.7
8254 Timers (D31:F0) ..................................................................................... 135
5.7.1
5.7.2
8259 Interrupt Controllers (PIC) (D31:F0) .......................................................... 139
5.8.1
5.8.2
5.8.3
5.8.4
5.8.5
5.8.6
Advanced Programmable Interrupt Controller (APIC) (D31:F0) .............................. 146
5.9.1
5.9.2
5.9.3
5.9.4
Serial Interrupt (D31:F0) ................................................................................. 149
5.10.1 Start Frame......................................................................................... 149
5.10.2 Data Frames........................................................................................ 150
5.10.3 Stop Frame ......................................................................................... 150
5.10.4 Specific Interrupts Not Supported via SERIRQ .......................................... 150
5.10.5 Data Frame Format .............................................................................. 151
Software Commands............................................................................. 132
Asserting DMA Requests........................................................................ 132
Abandoning DMA Requests .................................................................... 133
General Flow of DMA Transfers............................................................... 133
Terminal Count .................................................................................... 133
Verify Mode ......................................................................................... 134
DMA Request Deassertion...................................................................... 134
SYNC Field / LDRQ# Rules..................................................................... 135
Timer Programming .............................................................................. 136
Reading from the Interval Timer............................................................. 137
5.7.2.1
5.7.2.2
5.7.2.3
Interrupt Handling................................................................................ 140
5.8.1.1
5.8.1.2
5.8.1.3
Initialization Command Words (ICWx) ..................................................... 141
5.8.2.1
5.8.2.2
5.8.2.3
5.8.2.4
Operation Command Words (OCW) ......................................................... 142
Modes of Operation .............................................................................. 143
5.8.4.1
5.8.4.2
5.8.4.3
5.8.4.4
5.8.4.5
5.8.4.6
5.8.4.7
5.8.4.8
5.8.4.9
5.8.4.10 Automatic End of Interrupt Mode .............................................. 145
Masking Interrupts ............................................................................... 145
5.8.5.1
5.8.5.2
Steering PCI Interrupts ......................................................................... 145
Interrupt Handling................................................................................ 146
Interrupt Mapping ................................................................................ 146
PCI / PCI Express* Message-Based Interrupts .......................................... 147
Front Side Bus Interrupt Delivery ........................................................... 147
5.9.4.1
5.9.4.2
5.9.4.3
5.9.4.4
Simple Read........................................................................... 137
Counter Latch Command.......................................................... 137
Read Back Command .............................................................. 138
Generating Interrupts.............................................................. 140
Acknowledging Interrupts ........................................................ 140
Hardware/Software Interrupt Sequence ..................................... 141
ICW1 .................................................................................... 141
ICW2 .................................................................................... 142
ICW3 .................................................................................... 142
ICW4 .................................................................................... 142
Fully Nested Mode................................................................... 143
Special Fully-Nested Mode........................................................ 143
Automatic Rotation Mode (Equal Priority Devices)........................ 143
Poll Mode............................................................................... 144
Cascade Mode ........................................................................ 144
Edge and Level Triggered Mode ................................................ 144
End of Interrupt (EOI) Operations ............................................. 144
Normal End of Interrupt........................................................... 144
Masking on an Individual Interrupt Request................................ 145
Special Mask Mode.................................................................. 145
Edge-Triggered Operation ........................................................ 148
Level-Triggered Operation........................................................ 148
Interrupt Message Format ........................................................ 148
Specific Rotation Mode (Specific Priority).................................... 143
Registers Associated with Front Side Bus Interrupt Delivery.......... 148
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