NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 301

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chipset Configuration Registers
7.1.69
Intel
®
ICH8 Family Datasheet
GCS—General Control and Status Register
Offset Address: 3410–3413h
Default Value:
(Desktop
(Mobile
(Mobile
31:12
11:10
only)
only)
only)
7:6
Bit
9
8
7
6
Reserved
Boot BIOS Straps (BBS): This field determines the destination of accesses to the
BIOS memory range. The default values for these bits represent the strap values of
GNT0# (bit 11) and SPI_CS1# (bit 10) at the rising edge of PWROK.
When PCI is selected, the top 16MB of memory below 4GB (FF00_0000h to
FFFF_FFFFh) is accepted by the primary side of the PCI P2P bridge and forwarded
to the PCI bus. This allows systems with corrupted or unprogrammed flash to boot
from a PCI device. The PCI-to-PCI bridge Memory Space Enable bit does not need
to be set (nor any other bits) in order for these cycles to go to PCI. Note that BIOS
decode range bits and the other BIOS protection bits have no effect when PCI is
selected.
When SPI or LPC is selected, the range that is decoded is further qualified by other
configuration bits described in the respective sections.
The value in this field can be overwritten by software as long as the BIOS Interface
Lock-Down (bit 0) is not set.
NOTE: Boot BIOS Destination Select to LPC/PCI by functional strap or via Boot
Server Error Reporting Mode (SERM) — R/W.
0 = The Intel
1 = The (G)MCH is the final target of all errors from PCI Express* and DMI. In this
Reserved
Mobile IDE Configuration Lock Down (MICLD) — R/WLO.
0 = Disabled.
1 = BUC.PRS (offset 3414h, bit 1) is locked and cannot be written until a system
Reserved
FERR# MUX Enable (FME) — R/W. This bit enables FERR# to be a processor
break event indication. See
0 = Disabled.
1 = The ICH8 examines FERR# during a C2, C3, or C4 state as a break event.
Bits 11:10
to the ICH8 for the purpose of generating NMI.
mode, if the ICH8 detects a fatal, non-fatal, or correctable error on DMI or its
downstream ports, it sends a message to the (G)MCH. If the ICH8 receives an
ERR_* message from the downstream port, it sends that message to the
(G)MCH.
reset occurs. This prevents rogue software from changing the default state of
the PATA pins during boot after BIOS configures them. This bit is write once,
and is cleared by system reset and when returning from the S3/S4/S5 states.
00000yy0h (yy = xx0000x0b)
0xb
10b
11b
BIOS Destination Bit will not affect SPI accesses initiated by ME or
Integrated GbE LAN.
®
ICH8 is the final target of all errors. The (G)MCH sends a messages
Description
SPI
PCI
LPC
Chapter 5.13.5
Description
Attribute:
Size:
for a functional description.
R/W, R/WLO
32-bit
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