NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 425

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

LPC Interface Bridge Registers (D31:F0)
9.10.3
9.10.4
Intel
®
ICH8 Family Datasheet
GP_LVL—GPIO Level for Input or Output Register
Offset Address: GPIOBASE +0Ch
Default Value:
Lockable:
GPIO_USE_SEL Override Register (LOW)—GPIO Use Select
Override Register Low
Offset Address: GPIOBASE +10h
Default Value:
Lockable:
31:0
31:0
Bit
Bit
GP_LVL[31:0]— R/W:
If GPIO[n] is programmed to be an output (via the corresponding bit in the
GP_IO_SEL register), then the corresponding GP_LVL[n] bit can be updated by
software to drive a high or low value on the output pin. 1 = high, 0 = low.
If GPIO[n] is programmed as an input, then the corresponding GP_LVL bit reflects the
state of the input signal (1 = high, 0 = low.) and writes will have no effect.
When configured in native mode (GPIO_USE_SEL[n] is 0), writes to these bits have
no effect. The value reported in this register is undefined when programmed as
native mode.
GPIO_USE_SEL Override [31:0] — R/W. Each bit in this register enables the
corresponding GPIO (if it exists) to be used as a GPIO, rather than for the native
function.
0 = Signal used as native function.
1 = Signal used as a GPIO.
Once a bit is set to 1b, it can only be cleared a reset. Bits 31:24 and 15:8 are cleared
by RSMRST# and CF9h events. Bits 23:16 and 7:0 are cleared by PLTRST# events.
If the corresponding GPIO is not multiplexed with Native functionality or not
implemented at all, this bit has no effect.
This register corresponds to GPIO[31:0].
02FE8000h
No
00000000h
No
Description
Description
Attribute:
Size:
Power Well:
Attribute:
Size:
Power Well:
R/W
32-bit
Core for 0:7, 16:23,
Resume for 8:15, 24:31
R/W
32-bit
Core for 0:7, 16:23,
Resume for 8:15, 24:31
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