NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 611

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

EHCI Controller Registers (D29:F7, D26:F7)
Intel
®
ICH8 Family Datasheet
Bit
4
3
2
1
0
Host System Error — R/WC.
0 = No serious error occurred during a host system access involving the Host controller
1 = The Host controller sets this bit to 1 when a serious error occurs during a host
Frame List Rollover — R/WC.
0 = No Frame List Index rollover from its maximum value to 0.
1 = The Host controller sets this bit to a 1 when the Frame List Index (see Section) rolls
Port Change Detect — R/WC. This bit is allowed to be maintained in the Auxiliary
power well. Alternatively, it is also acceptable that on a D3 to D0 transition of the EHCI
HC device, this bit is loaded with the OR of all of the PORTSC change bits (including:
Force port resume, overcurrent change, enable/disable change and connect status
change). Regardless of the implementation, when this bit is readable (i.e., in the D0
state), it must provide a valid view of the Port Status registers.
0 = No change bit transition from a 0 to 1 or No Force Port Resume bit transition from 0
1 = The Host controller sets this bit to 1 when any port for which the Port Owner bit is
USB Error Interrupt (USBERRINT) — R/WC.
0 = No error condition.
1 = The Host controller sets this bit to 1 when completion of a USB transaction results in
USB Interrupt (USBINT) — R/WC.
0 = No completion of a USB transaction whose Transfer Descriptor had its IOC bit set.
1 = The Host controller sets this bit to 1 when the cause of an interrupt is a completion
module
system access involving the Host controller module. A hardware interrupt is
generated to the system. Memory read cycles initiated by the EHC that receive any
status other than Successful will result in this bit being set.
When this error occurs, the Host controller clears the Run/Stop bit in the
USB2.0_CMDregister (D29:F7, D26:F7:CAPLENGTH + 20h, bit 0) to prevent further
execution of the scheduled TDs. A hardware interrupt is generated to the system (if
enabled in the Interrupt Enable Register).
over from its maximum value to 0. Since the ICH8 only supports the 1024-entry
Frame List Size, the Frame List Index rolls over every time FRNUM13 toggles.
to 1 as a result of a J-K transition detected on a suspended port.
set to 0 has a change bit transition from a 0 to 1 or a Force Port Resume bit
transition from 0 to 1 as a result of a J-K transition detected on a suspended port.
an error condition (e.g., error counter underflow). If the TD on which the error
interrupt occurred also had its IOC bit set, both this bit and Bit 0 are set. See the
EHCI specification for a list of the USB errors that will result in this interrupt being
asserted.
No short packet is detected.
of a USB transaction whose Transfer Descriptor had its IOC bit set.
The Host controller also sets this bit to 1 when a short packet is detected (actual
number of bytes received was less than the expected number of bytes).
Description
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