NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 446

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10.1.24
10.1.25
446
SVCAP—Subsystem Vendor Capability Register
(PCI-PCI—D30:F0)
Offset Address: 50h
Default Value:
SVID—Subsystem Vendor IDs Register (PCI-PCI—D30:F0)
Offset Address: 54h
Default Value:
31:16
15:8
15:0
7:0
Bit
Bit
Bit
2
1
0
Next Capability (NEXT) — RO. Value of 00h indicates this is the last item in the list.
Capability Identifier (CID) — RO. Value of 0Dh indicates this is a PCI bridge subsystem
vendor capability.
Subsystem Identifier (SID) — R/WO. Indicates the subsystem as identified by the
vendor. This field is write once and is locked down until a bridge reset occurs (not the
PCI bus reset).
Subsystem Vendor Identifier (SVID) — R/WO. Indicates the manufacturer of the
subsystem. This field is write once and is locked down until a bridge reset occurs (not
the PCI bus reset).
Peer Decode Enable (PDE) — R/W.
0 = The PCI bridge assumes that all memory cycles target main memory, and all I/O
1 = The PCI bridge will perform peer decode on any memory or I/O cycle from PCI that
Reserved
Received Target Abort SERR# Enable (RTAE) — R/W. When set, the PCI bridge will
report SERR# when PSTS.RTA (D30:F0:06 bit 12) or SSTS.RTA (D30:F0:1E bit 12) are
set, and CMD.SEE (D30:F0:04 bit 8) is set.
cycles are not claimed.
falls outside of the memory and I/O window registers
000Dh
00000000h
–
–
51h
57h
§ §
Description
Description
Description
Attribute:
Size:
Attribute:
Size:
PCI-to-PCI Bridge Registers (D30:F0)
RO
16 bits
R/WO
32 bits
Intel
®
ICH8 Family Datasheet