NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 614

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

15.2.2.5
15.2.2.6
614
CTRLDSSEGMENT—Control Data Structure Segment
Register
Offset:
Default Value:
This 32-bit register corresponds to the most significant address bits [63:32] for all
EHCI data structures. Since the ICH8 hardwires the 64-bit Addressing Capability field in
HCCPARAMS to 1, then this register is used with the link pointers to construct 64-bit
addresses to EHCI control data structures. This register is concatenated with the link
pointer from either the PERIODICLISTBASE, ASYNCLISTADDR, or any control data
structure link field to construct a 64-bit address. This register allows the host software
to locate all control data structures within the same 4 GB memory segment.
PERIODICLISTBASE—Periodic Frame List Base Address
Register
Offset:
Default Value:
This 32-bit register contains the beginning address of the Periodic Frame List in the
system memory. Since the ICH8 host controller operates in 64-bit mode (as indicated
by the 1 in the 64-bit Addressing Capability field in the HCCSPARAMS register) (offset
08h, bit 0), then the most significant 32 bits of every control data structure address
comes from the CTRLDSSEGMENT register. HCD loads this register prior to starting the
schedule execution by the host controller. The memory structure referenced by this
physical memory pointer is assumed to be 4-Kbyte aligned. The contents of this
register are combined with the Frame Index Register (FRINDEX) to enable the Host
controller to step through the Periodic Frame List in sequence.
31:12
31:12
11:0
11:0
Bit
Bit
Upper Address[63:44] — RO. Hardwired to 0s. The ICH8 EHC is only capable of
generating addresses up to 16 terabytes (44 bits of address).
Upper Address[43:32] — R/W. This 12-bit field corresponds to address bits 43:32 when
forming a control data structure address.
Base Address (Low) — R/W. These bits correspond to memory address signals
[31:12], respectively.
Reserved. Must be written as 0s. During runtime, the value of these bits are undefined.
MEM_BASE + 30h–33h
00000000h
MEM_BASE + 34h–37h
00000000h
Description
Description
Attribute:
Size:
Attribute:
Size:
EHCI Controller Registers (D29:F7, D26:F7)
R/W, RO
32 bits
R/W
32 bits
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ICH8 Family Datasheet