NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 557

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SATA Controller Registers (D31:F5)
13.2.1
Intel
®
ICH8 Family Datasheet
BMIC[P,S]—Bus Master IDE Command Register (D31:F5)
Address Offset: Primary: BAR + 00h
Default Value:
7:4
2:1
Bit
3
0
Reserved. Returns 0.
Read / Write Control (R/WC) — R/W. This bit sets the direction of the bus master
transfer: This bit must NOT be changed when the bus master function is active.
0 = Memory reads
1 = Memory writes
Reserved. Returns 0.
Start/Stop Bus Master (START) — R/W.
0 = All state information is lost when this bit is cleared. Master mode operation cannot
1 = Enables bus master operation of the controller. Bus master operation does not
NOTE: This bit is intended to be cleared by software after the data transfer is
be stopped and then resumed. If this bit is reset while bus master operation is still
active (i.e., the Bus Master IDE Active bit (D31:F5:BAR + 02h, bit 0) of the Bus
Master IDE Status register for that IDE channel is set) and the drive has not yet
finished its data transfer (the Interrupt bit in the Bus Master IDE Status register for
that IDE channel is not set), the bus master command is said to be aborted and
data transferred from the drive may be discarded instead of being written to
system memory.
actually start unless the Bus Master Enable bit (D31:F1:04h, bit 2) in PCI
configuration space is also set. Bus master operation begins when this bit is
detected changing from 0 to 1. The controller will transfer data between the IDE
device and memory only when this bit is set. Master operation can be halted by
writing a 0 to this bit.
completed, as indicated by either the Bus Master IDE Active bit being cleared or
the Interrupt bit of the Bus Master IDE Status register for that IDE channel
being set, or both. Hardware does not clear this bit automatically. If this bit is
cleared to 0 prior to the DMA data transfer being initiated by the drive in a
Secondary: BAR + 08h
00h
Description
Attribute:
Size:
R/W
8 bits
557